diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs
index af13cb70c0..fa7aa4ea60 100644
--- a/cranelift/codegen/src/isa/aarch64/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/mod.rs
@@ -66,6 +66,7 @@ impl MachBackend for AArch64Backend {
         let buffer = vcode.emit();
         let frame_size = vcode.frame_size();
         let unwind_info = vcode.unwind_info()?;
+        let stackslot_offsets = vcode.stackslot_offsets().clone();
 
         let disasm = if want_disasm {
             Some(vcode.show_rru(Some(&create_reg_universe(flags))))
@@ -81,6 +82,7 @@ impl MachBackend for AArch64Backend {
             disasm,
             unwind_info,
             value_labels_ranges: None,
+            stackslot_offsets,
         })
     }
 
diff --git a/cranelift/codegen/src/isa/arm32/mod.rs b/cranelift/codegen/src/isa/arm32/mod.rs
index 3976d74ba6..da557c4beb 100644
--- a/cranelift/codegen/src/isa/arm32/mod.rs
+++ b/cranelift/codegen/src/isa/arm32/mod.rs
@@ -61,6 +61,7 @@ impl MachBackend for Arm32Backend {
         let vcode = self.compile_vcode(func, flags.clone())?;
         let buffer = vcode.emit();
         let frame_size = vcode.frame_size();
+        let stackslot_offsets = vcode.stackslot_offsets().clone();
 
         let disasm = if want_disasm {
             Some(vcode.show_rru(Some(&create_reg_universe())))
@@ -76,6 +77,7 @@ impl MachBackend for Arm32Backend {
             disasm,
             unwind_info: None,
             value_labels_ranges: None,
+            stackslot_offsets,
         })
     }
 
diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs
index 28cd503615..6b3054a643 100644
--- a/cranelift/codegen/src/isa/x64/mod.rs
+++ b/cranelift/codegen/src/isa/x64/mod.rs
@@ -62,7 +62,8 @@ impl MachBackend for X64Backend {
         let buffer = buffer.finish();
         let frame_size = vcode.frame_size();
         let unwind_info = vcode.unwind_info()?;
-        let value_labels_ranges = vcode.value_labels_ranges()?;
+        let value_labels_ranges = vcode.value_labels_ranges();
+        let stackslot_offsets = vcode.stackslot_offsets().clone();
 
         let disasm = if want_disasm {
             Some(vcode.show_rru(Some(&create_reg_universe_systemv(flags))))
@@ -76,6 +77,7 @@ impl MachBackend for X64Backend {
             disasm,
             unwind_info,
             value_labels_ranges,
+            stackslot_offsets,
         })
     }
 
diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs
index ca4b2414df..5a3c267b15 100644
--- a/cranelift/codegen/src/machinst/abi.rs
+++ b/cranelift/codegen/src/machinst/abi.rs
@@ -57,6 +57,9 @@ pub trait ABICallee {
     /// Number of stack slots (not spill slots).
     fn num_stackslots(&self) -> usize;
 
+    /// The offsets of all stack slots (not spill slots) for debuginfo purposes.
+    fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32>;
+
     /// Generate an instruction which copies an argument to a destination
     /// register.
     fn gen_copy_arg_to_regs(
diff --git a/cranelift/codegen/src/machinst/abi_impl.rs b/cranelift/codegen/src/machinst/abi_impl.rs
index 439e93e2d9..a0d4634078 100644
--- a/cranelift/codegen/src/machinst/abi_impl.rs
+++ b/cranelift/codegen/src/machinst/abi_impl.rs
@@ -506,7 +506,7 @@ pub struct ABICalleeImpl<M: ABIMachineSpec> {
     /// Signature: arg and retval regs.
     sig: ABISig,
     /// Offsets to each stackslot.
-    stackslots: Vec<u32>,
+    stackslots: PrimaryMap<StackSlot, u32>,
     /// Total stack size of all stackslots.
     stackslots_size: u32,
     /// Stack size to be reserved for outgoing arguments.
@@ -584,7 +584,7 @@ impl<M: ABIMachineSpec> ABICalleeImpl<M> {
 
         // Compute stackslot locations and total stackslot size.
         let mut stack_offset: u32 = 0;
-        let mut stackslots = vec![];
+        let mut stackslots = PrimaryMap::new();
         for (stackslot, data) in f.stack_slots.iter() {
             let off = stack_offset;
             stack_offset += data.size;
@@ -926,6 +926,10 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
         self.stackslots.len()
     }
 
+    fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32> {
+        &self.stackslots
+    }
+
     fn gen_copy_arg_to_regs(
         &self,
         idx: usize,
@@ -1101,7 +1105,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
     ) -> SmallInstVec<Self::I> {
         // Offset from beginning of stackslot area, which is at nominal SP (see
         // [MemArg::NominalSPOffset] for more details on nominal SP tracking).
-        let stack_off = self.stackslots[slot.as_u32() as usize] as i64;
+        let stack_off = self.stackslots[slot] as i64;
         let sp_off: i64 = stack_off + (offset as i64);
         trace!("load_stackslot: slot {} -> sp_off {}", slot, sp_off);
         gen_load_stack_multi::<M>(StackAMode::NominalSPOffset(sp_off, ty), into_regs, ty)
@@ -1117,7 +1121,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
     ) -> SmallInstVec<Self::I> {
         // Offset from beginning of stackslot area, which is at nominal SP (see
         // [MemArg::NominalSPOffset] for more details on nominal SP tracking).
-        let stack_off = self.stackslots[slot.as_u32() as usize] as i64;
+        let stack_off = self.stackslots[slot] as i64;
         let sp_off: i64 = stack_off + (offset as i64);
         trace!("store_stackslot: slot {} -> sp_off {}", slot, sp_off);
         gen_store_stack_multi::<M>(StackAMode::NominalSPOffset(sp_off, ty), from_regs, ty)
@@ -1127,7 +1131,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
     fn stackslot_addr(&self, slot: StackSlot, offset: u32, into_reg: Writable<Reg>) -> Self::I {
         // Offset from beginning of stackslot area, which is at nominal SP (see
         // [MemArg::NominalSPOffset] for more details on nominal SP tracking).
-        let stack_off = self.stackslots[slot.as_u32() as usize] as i64;
+        let stack_off = self.stackslots[slot] as i64;
         let sp_off: i64 = stack_off + (offset as i64);
         M::gen_get_stack_addr(StackAMode::NominalSPOffset(sp_off, I8), into_reg, I8)
     }
diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs
index c7e86437fa..daece77ab5 100644
--- a/cranelift/codegen/src/machinst/mod.rs
+++ b/cranelift/codegen/src/machinst/mod.rs
@@ -62,7 +62,7 @@
 
 use crate::binemit::{CodeInfo, CodeOffset, StackMap};
 use crate::ir::condcodes::IntCC;
-use crate::ir::{Function, SourceLoc, Type, ValueLabel};
+use crate::ir::{Function, SourceLoc, StackSlot, Type, ValueLabel};
 use crate::isa::unwind::input as unwind_input;
 use crate::result::CodegenResult;
 use crate::settings::Flags;
@@ -71,6 +71,7 @@ use alloc::boxed::Box;
 use alloc::vec::Vec;
 use core::fmt::Debug;
 use core::ops::Range;
+use cranelift_entity::PrimaryMap;
 use regalloc::RegUsageCollector;
 use regalloc::{
     RealReg, RealRegUniverse, Reg, RegClass, RegUsageMapper, SpillSlot, VirtualReg, Writable,
@@ -343,6 +344,8 @@ pub struct MachCompileResult {
     pub unwind_info: Option<unwind_input::UnwindInfo<Reg>>,
     /// Debug info: value labels to registers/stackslots at code offsets.
     pub value_labels_ranges: Option<ValueLabelsRanges>,
+    /// Debug info: stackslots to stack pointer offsets.
+    pub stackslot_offsets: PrimaryMap<StackSlot, u32>,
 }
 
 impl MachCompileResult {
diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs
index ab1cca0f47..cb81610e95 100644
--- a/cranelift/codegen/src/machinst/vcode.rs
+++ b/cranelift/codegen/src/machinst/vcode.rs
@@ -617,17 +617,18 @@ impl<I: VCodeInst> VCode<I> {
     }
 
     /// Generates value-label ranges.
-    pub fn value_labels_ranges(&self) -> crate::result::CodegenResult<Option<ValueLabelsRanges>> {
+    pub fn value_labels_ranges(&self) -> Option<ValueLabelsRanges> {
         if !self.has_value_labels {
-            return Ok(None);
+            return None;
         }
 
         let layout = &self.insts_layout.borrow();
-        Ok(Some(debug::compute(
-            &self.insts,
-            &layout.0[..],
-            &layout.1[..],
-        )))
+        Some(debug::compute(&self.insts, &layout.0[..], &layout.1[..]))
+    }
+
+    /// Get the offsets of stackslots.
+    pub fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32> {
+        self.abi.stackslot_offsets()
     }
 
     /// Get the IR block for a BlockIndex, if one exists.