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[machinst x64]: add avg_round implementation

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This commit is contained in:
Andrew Brown
2020-09-21 11:49:26 -07:00
parent b202464fa0
commit 7546d98844
4 changed files with 26 additions and 0 deletions
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6
cranelift/codegen/src/isa/x64/inst/args.rs
View File

@@ -401,6 +401,8 @@ pub enum SseOpcode {
Paddd, Paddd,
Paddq, Paddq,
Paddw, Paddw,
Pavgb,
Pavgw,
Pmulld, Pmulld,
Pmullw, Pmullw,
Pmuludq, Pmuludq,
@@ -503,6 +505,8 @@ impl SseOpcode {
| SseOpcode::Paddd | SseOpcode::Paddd
| SseOpcode::Paddq | SseOpcode::Paddq
| SseOpcode::Paddw | SseOpcode::Paddw
| SseOpcode::Pavgb
| SseOpcode::Pavgw
| SseOpcode::Pmullw | SseOpcode::Pmullw
| SseOpcode::Pmuludq | SseOpcode::Pmuludq
| SseOpcode::Psllw | SseOpcode::Psllw
@@ -603,6 +607,8 @@ impl fmt::Debug for SseOpcode {
SseOpcode::Paddd => "paddd", SseOpcode::Paddd => "paddd",
SseOpcode::Paddq => "paddq", SseOpcode::Paddq => "paddq",
SseOpcode::Paddw => "paddw", SseOpcode::Paddw => "paddw",
SseOpcode::Pavgb => "pavgb",
SseOpcode::Pavgw => "pavgw",
SseOpcode::Pmulld => "pmulld", SseOpcode::Pmulld => "pmulld",
SseOpcode::Pmullw => "pmullw", SseOpcode::Pmullw => "pmullw",
SseOpcode::Pmuludq => "pmuludq", SseOpcode::Pmuludq => "pmuludq",

2
cranelift/codegen/src/isa/x64/inst/emit.rs
View File

@@ -1778,6 +1778,8 @@ pub(crate) fn emit(
SseOpcode::Paddd => (LegacyPrefixes::_66, 0x0FFE, 2), SseOpcode::Paddd => (LegacyPrefixes::_66, 0x0FFE, 2),
SseOpcode::Paddq => (LegacyPrefixes::_66, 0x0FD4, 2), SseOpcode::Paddq => (LegacyPrefixes::_66, 0x0FD4, 2),
SseOpcode::Paddw => (LegacyPrefixes::_66, 0x0FFD, 2), SseOpcode::Paddw => (LegacyPrefixes::_66, 0x0FFD, 2),
SseOpcode::Pavgb => (LegacyPrefixes::_66, 0x0FE0, 2),
SseOpcode::Pavgw => (LegacyPrefixes::_66, 0x0FE3, 2),
SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3), SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3),
SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2), SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2),
SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2), SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2),

12
cranelift/codegen/src/isa/x64/inst/emit_tests.rs
View File

@@ -3111,6 +3111,18 @@ fn test_x64_emit() {
"paddq %xmm1, %xmm8", "paddq %xmm1, %xmm8",
)); ));
insns.push((
Inst::xmm_rm_r(SseOpcode::Pavgb, RegMem::reg(xmm12), w_xmm13),
"66450FE0EC",
"pavgb %xmm12, %xmm13",
));
insns.push((
Inst::xmm_rm_r(SseOpcode::Pavgw, RegMem::reg(xmm1), w_xmm8),
"66440FE3C1",
"pavgw %xmm1, %xmm8",
));
insns.push(( insns.push((
Inst::xmm_rm_r(SseOpcode::Psubb, RegMem::reg(xmm5), w_xmm9), Inst::xmm_rm_r(SseOpcode::Psubb, RegMem::reg(xmm5), w_xmm9),
"66440FF8CD", "66440FF8CD",

6
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -508,6 +508,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
| Opcode::IaddIfcout | Opcode::IaddIfcout
| Opcode::Isub | Opcode::Isub
| Opcode::Imul | Opcode::Imul
| Opcode::AvgRound
| Opcode::Band | Opcode::Band
| Opcode::Bor | Opcode::Bor
| Opcode::Bxor => { | Opcode::Bxor => {
@@ -634,6 +635,11 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
} }
_ => panic!("Unsupported type for packed Imul instruction"), _ => panic!("Unsupported type for packed Imul instruction"),
}, },
Opcode::AvgRound => match ty {
types::I8X16 => SseOpcode::Pavgb,
types::I16X8 => SseOpcode::Pavgw,
_ => panic!("Unsupported type for packed AvgRound instruction: {}", ty),
},
_ => panic!("Unsupported packed instruction"), _ => panic!("Unsupported packed instruction"),
}; };
let lhs = put_input_in_reg(ctx, inputs[0]); let lhs = put_input_in_reg(ctx, inputs[0]);