diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs
index 18e5d15d46..caa00eed3d 100644
--- a/cranelift/codegen/src/isa/x64/inst/args.rs
+++ b/cranelift/codegen/src/isa/x64/inst/args.rs
@@ -401,6 +401,8 @@ pub enum SseOpcode {
     Paddd,
     Paddq,
     Paddw,
+    Pavgb,
+    Pavgw,
     Pmulld,
     Pmullw,
     Pmuludq,
@@ -503,6 +505,8 @@ impl SseOpcode {
             | SseOpcode::Paddd
             | SseOpcode::Paddq
             | SseOpcode::Paddw
+            | SseOpcode::Pavgb
+            | SseOpcode::Pavgw
             | SseOpcode::Pmullw
             | SseOpcode::Pmuludq
             | SseOpcode::Psllw
@@ -603,6 +607,8 @@ impl fmt::Debug for SseOpcode {
             SseOpcode::Paddd => "paddd",
             SseOpcode::Paddq => "paddq",
             SseOpcode::Paddw => "paddw",
+            SseOpcode::Pavgb => "pavgb",
+            SseOpcode::Pavgw => "pavgw",
             SseOpcode::Pmulld => "pmulld",
             SseOpcode::Pmullw => "pmullw",
             SseOpcode::Pmuludq => "pmuludq",
diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs
index 5aaca4e65b..399d091198 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit.rs
@@ -1778,6 +1778,8 @@ pub(crate) fn emit(
                 SseOpcode::Paddd => (LegacyPrefixes::_66, 0x0FFE, 2),
                 SseOpcode::Paddq => (LegacyPrefixes::_66, 0x0FD4, 2),
                 SseOpcode::Paddw => (LegacyPrefixes::_66, 0x0FFD, 2),
+                SseOpcode::Pavgb => (LegacyPrefixes::_66, 0x0FE0, 2),
+                SseOpcode::Pavgw => (LegacyPrefixes::_66, 0x0FE3, 2),
                 SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3),
                 SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2),
                 SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2),
diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
index 866d2e305c..269922b764 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
@@ -3111,6 +3111,18 @@ fn test_x64_emit() {
         "paddq   %xmm1, %xmm8",
     ));
 
+    insns.push((
+        Inst::xmm_rm_r(SseOpcode::Pavgb, RegMem::reg(xmm12), w_xmm13),
+        "66450FE0EC",
+        "pavgb   %xmm12, %xmm13",
+    ));
+
+    insns.push((
+        Inst::xmm_rm_r(SseOpcode::Pavgw, RegMem::reg(xmm1), w_xmm8),
+        "66440FE3C1",
+        "pavgw   %xmm1, %xmm8",
+    ));
+
     insns.push((
         Inst::xmm_rm_r(SseOpcode::Psubb, RegMem::reg(xmm5), w_xmm9),
         "66440FF8CD",
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 474a6d86c3..22c1a7720d 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -508,6 +508,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
         | Opcode::IaddIfcout
         | Opcode::Isub
         | Opcode::Imul
+        | Opcode::AvgRound
         | Opcode::Band
         | Opcode::Bor
         | Opcode::Bxor => {
@@ -634,6 +635,11 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                         }
                         _ => panic!("Unsupported type for packed Imul instruction"),
                     },
+                    Opcode::AvgRound => match ty {
+                        types::I8X16 => SseOpcode::Pavgb,
+                        types::I16X8 => SseOpcode::Pavgw,
+                        _ => panic!("Unsupported type for packed AvgRound instruction: {}", ty),
+                    },
                     _ => panic!("Unsupported packed instruction"),
                 };
                 let lhs = put_input_in_reg(ctx, inputs[0]);