[machinst x64]: add avg_round implementation
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@@ -401,6 +401,8 @@ pub enum SseOpcode {
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Paddd,
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Paddq,
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Paddw,
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Pavgb,
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Pavgw,
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Pmulld,
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Pmullw,
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Pmuludq,
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@@ -503,6 +505,8 @@ impl SseOpcode {
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| SseOpcode::Paddd
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| SseOpcode::Paddq
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| SseOpcode::Paddw
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| SseOpcode::Pavgb
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| SseOpcode::Pavgw
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| SseOpcode::Pmullw
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| SseOpcode::Pmuludq
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| SseOpcode::Psllw
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@@ -603,6 +607,8 @@ impl fmt::Debug for SseOpcode {
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SseOpcode::Paddd => "paddd",
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SseOpcode::Paddq => "paddq",
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SseOpcode::Paddw => "paddw",
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SseOpcode::Pavgb => "pavgb",
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SseOpcode::Pavgw => "pavgw",
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SseOpcode::Pmulld => "pmulld",
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SseOpcode::Pmullw => "pmullw",
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SseOpcode::Pmuludq => "pmuludq",
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@@ -1778,6 +1778,8 @@ pub(crate) fn emit(
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SseOpcode::Paddd => (LegacyPrefixes::_66, 0x0FFE, 2),
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SseOpcode::Paddq => (LegacyPrefixes::_66, 0x0FD4, 2),
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SseOpcode::Paddw => (LegacyPrefixes::_66, 0x0FFD, 2),
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SseOpcode::Pavgb => (LegacyPrefixes::_66, 0x0FE0, 2),
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SseOpcode::Pavgw => (LegacyPrefixes::_66, 0x0FE3, 2),
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SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3),
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SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2),
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SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2),
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@@ -3111,6 +3111,18 @@ fn test_x64_emit() {
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"paddq %xmm1, %xmm8",
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));
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insns.push((
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Inst::xmm_rm_r(SseOpcode::Pavgb, RegMem::reg(xmm12), w_xmm13),
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"66450FE0EC",
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"pavgb %xmm12, %xmm13",
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));
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insns.push((
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Inst::xmm_rm_r(SseOpcode::Pavgw, RegMem::reg(xmm1), w_xmm8),
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"66440FE3C1",
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"pavgw %xmm1, %xmm8",
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));
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insns.push((
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Inst::xmm_rm_r(SseOpcode::Psubb, RegMem::reg(xmm5), w_xmm9),
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"66440FF8CD",
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