Adds support for legalizing CLZ, CTZ and POPCOUNT on baseline x86_64 targets.
Changes: * Adds a new generic instruction, SELECTIF, that does value selection (a la conditional move) similarly to existing SELECT, except that it is controlled by condition code input and flags-register inputs. * Adds a new Intel x86_64 variant, 'baseline', that supports SSE2 and nothing else. * Adds new Intel x86_64 instructions BSR and BSF. * Implements generic CLZ, CTZ and POPCOUNT on x86_64 'baseline' targets using the new BSR, BSF and SELECTIF instructions. * Implements SELECTIF on x86_64 targets using conditional-moves. * new test filetests/isa/intel/baseline_clz_ctz_popcount.cton (for legalization) * new test filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton (for encoding) * Allow lib/cretonne/meta/gen_legalizer.py to generate non-snake-caseified Rust without rustc complaining. Fixes #238.
This commit is contained in:
Julian Seward
committed by
Jakob Stoklund Olesen
Jakob Stoklund Olesen
parent
e3714ddd10
commit
6f8a54b6a5
@@ -367,6 +367,17 @@ enc_i32_i64(base.ifcmp, r.rcmp, 0x39)
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enc_both(base.trueif, r.seti_abcd, 0x0f, 0x90)
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enc_both(base.trueff, r.setf_abcd, 0x0f, 0x90)
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#
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# Conditional move (a.k.a integer select)
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#
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enc_i32_i64(base.selectif, r.cmov, 0x0F, 0x40)
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#
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# Bit scan forwards and reverse
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#
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enc_i32_i64(x86.bsf, r.bsf_and_bsr, 0x0F, 0xBC)
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enc_i32_i64(x86.bsr, r.bsf_and_bsr, 0x0F, 0xBD)
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#
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# Convert bool to int.
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#
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@@ -5,6 +5,7 @@ This module defines additional instructions that are useful only to the Intel
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target ISA.
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"""
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from base.types import iflags
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from cdsl.operands import Operand
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from cdsl.typevar import TypeVar
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from cdsl.instructions import Instruction, InstructionGroup
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@@ -125,4 +126,26 @@ pop = Instruction(
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""",
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outs=x, can_load=True, other_side_effects=True)
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y = Operand('y', iWord)
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rflags = Operand('rflags', iflags)
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bsr = Instruction(
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'x86_bsr', r"""
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Bit Scan Reverse -- returns the bit-index of the most significant 1
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in the word. Result is undefined if the argument is zero. However, it
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sets the Z flag depending on the argument, so it is at least easy to
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detect and handle that case.
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This is polymorphic in i32 and i64. It is implemented for both i64 and
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i32 in 64-bit mode, and only for i32 in 32-bit mode.
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""",
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ins=x, outs=(y, rflags))
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bsf = Instruction(
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'x86_bsf', r"""
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Bit Scan Forwards -- returns the bit-index of the least significant 1
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in the word. Is otherwise identical to 'bsr', just above.
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""",
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ins=x, outs=(y, rflags))
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GROUP.close()
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@@ -4,7 +4,7 @@ Custom legalization patterns for Intel.
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from __future__ import absolute_import
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from cdsl.ast import Var
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from cdsl.xform import Rtl, XFormGroup
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from base.immediates import imm64, floatcc
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from base.immediates import imm64, intcc, floatcc
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from base.types import i32, i64
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from base import legalize as shared
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from base import instructions as insts
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@@ -100,3 +100,131 @@ intel_expand.custom_legalize(insts.fcvt_from_uint, 'expand_fcvt_from_uint')
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# Conversions from float to int can trap.
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intel_expand.custom_legalize(insts.fcvt_to_sint, 'expand_fcvt_to_sint')
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intel_expand.custom_legalize(insts.fcvt_to_uint, 'expand_fcvt_to_uint')
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# Count leading and trailing zeroes, for baseline x86_64
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c_minus_one = Var('c_minus_one')
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c_thirty_one = Var('c_thirty_one')
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c_thirty_two = Var('c_thirty_two')
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c_sixty_three = Var('c_sixty_three')
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c_sixty_four = Var('c_sixty_four')
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index1 = Var('index1')
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r2flags = Var('r2flags')
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index2 = Var('index2')
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intel_expand.legalize(
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a << insts.clz.i64(x),
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Rtl(
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c_minus_one << insts.iconst(imm64(-1)),
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c_sixty_three << insts.iconst(imm64(63)),
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(index1, r2flags) << x86.bsr(x),
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index2 << insts.selectif(intcc.eq, r2flags, c_minus_one, index1),
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a << insts.isub(c_sixty_three, index2),
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))
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intel_expand.legalize(
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a << insts.clz.i32(x),
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Rtl(
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c_minus_one << insts.iconst(imm64(-1)),
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c_thirty_one << insts.iconst(imm64(31)),
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(index1, r2flags) << x86.bsr(x),
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index2 << insts.selectif(intcc.eq, r2flags, c_minus_one, index1),
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a << insts.isub(c_thirty_one, index2),
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))
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intel_expand.legalize(
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a << insts.ctz.i64(x),
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Rtl(
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c_sixty_four << insts.iconst(imm64(64)),
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(index1, r2flags) << x86.bsf(x),
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a << insts.selectif(intcc.eq, r2flags, c_sixty_four, index1),
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))
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intel_expand.legalize(
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a << insts.ctz.i32(x),
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Rtl(
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c_thirty_two << insts.iconst(imm64(32)),
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(index1, r2flags) << x86.bsf(x),
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a << insts.selectif(intcc.eq, r2flags, c_thirty_two, index1),
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))
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# Population count for baseline x86_64
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qv1 = Var('qv1')
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qv3 = Var('qv3')
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qv4 = Var('qv4')
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qv5 = Var('qv5')
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qv6 = Var('qv6')
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qv7 = Var('qv7')
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qv8 = Var('qv8')
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qv9 = Var('qv9')
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qv10 = Var('qv10')
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qv11 = Var('qv11')
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qv12 = Var('qv12')
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qv13 = Var('qv13')
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qv14 = Var('qv14')
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qv15 = Var('qv15')
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qv16 = Var('qv16')
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qc77 = Var('qc77')
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qc0F = Var('qc0F')
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qc01 = Var('qc01')
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intel_expand.legalize(
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qv16 << insts.popcnt.i64(qv1),
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Rtl(
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qv3 << insts.ushr_imm(qv1, imm64(1)),
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qc77 << insts.iconst(imm64(0x7777777777777777)),
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qv4 << insts.band(qv3, qc77),
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qv5 << insts.isub(qv1, qv4),
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qv6 << insts.ushr_imm(qv4, imm64(1)),
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qv7 << insts.band(qv6, qc77),
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qv8 << insts.isub(qv5, qv7),
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qv9 << insts.ushr_imm(qv7, imm64(1)),
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qv10 << insts.band(qv9, qc77),
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qv11 << insts.isub(qv8, qv10),
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qv12 << insts.ushr_imm(qv11, imm64(4)),
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qv13 << insts.iadd(qv11, qv12),
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qc0F << insts.iconst(imm64(0x0F0F0F0F0F0F0F0F)),
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qv14 << insts.band(qv13, qc0F),
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qc01 << insts.iconst(imm64(0x0101010101010101)),
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qv15 << insts.imul(qv14, qc01),
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qv16 << insts.ushr_imm(qv15, imm64(56))
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))
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lv1 = Var('lv1')
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lv3 = Var('lv3')
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lv4 = Var('lv4')
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lv5 = Var('lv5')
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lv6 = Var('lv6')
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lv7 = Var('lv7')
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lv8 = Var('lv8')
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lv9 = Var('lv9')
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lv10 = Var('lv10')
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lv11 = Var('lv11')
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lv12 = Var('lv12')
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lv13 = Var('lv13')
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lv14 = Var('lv14')
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lv15 = Var('lv15')
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lv16 = Var('lv16')
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lc77 = Var('lc77')
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lc0F = Var('lc0F')
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lc01 = Var('lc01')
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intel_expand.legalize(
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lv16 << insts.popcnt.i32(lv1),
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Rtl(
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lv3 << insts.ushr_imm(lv1, imm64(1)),
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lc77 << insts.iconst(imm64(0x77777777)),
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lv4 << insts.band(lv3, lc77),
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lv5 << insts.isub(lv1, lv4),
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lv6 << insts.ushr_imm(lv4, imm64(1)),
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lv7 << insts.band(lv6, lc77),
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lv8 << insts.isub(lv5, lv7),
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lv9 << insts.ushr_imm(lv7, imm64(1)),
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lv10 << insts.band(lv9, lc77),
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lv11 << insts.isub(lv8, lv10),
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lv12 << insts.ushr_imm(lv11, imm64(4)),
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lv13 << insts.iadd(lv11, lv12),
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lc0F << insts.iconst(imm64(0x0F0F0F0F)),
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lv14 << insts.band(lv13, lc0F),
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lc01 << insts.iconst(imm64(0x01010101)),
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lv15 << insts.imul(lv14, lc01),
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lv16 << insts.ushr_imm(lv15, imm64(24))
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))
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@@ -8,6 +8,7 @@ from cdsl.registers import RegClass
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from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry, NullAry
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from base.formats import Trap, Call, IndirectCall, Store, Load
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from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
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from base.formats import IntSelect
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from base.formats import Jump, Branch, BranchInt, BranchFloat
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from base.formats import Ternary, FuncAddr, UnaryGlobalVar
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from base.formats import RegMove, RegSpill, RegFill, CopySpecial
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@@ -1021,6 +1022,32 @@ setf_abcd = TailRecipe(
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modrm_r_bits(out_reg0, bits, sink);
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''')
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#
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# Conditional move (a.k.a integer select)
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# (maybe-REX.W) 0F 4x modrm(r,r)
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# 1 byte, modrm(r,r), is after the opcode
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#
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cmov = TailRecipe(
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'cmov', IntSelect, size=1, ins=(FLAG.eflags, GPR, GPR), outs=2,
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requires_prefix=False,
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clobbers_flags=False,
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emit='''
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PUT_OP(bits | icc2opc(cond), rex2(in_reg1, in_reg2), sink);
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modrm_rr(in_reg1, in_reg2, sink);
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''')
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#
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# Bit scan forwards and reverse
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#
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bsf_and_bsr = TailRecipe(
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'bsf_and_bsr', Unary, size=1, ins=GPR, outs=(GPR, FLAG.eflags),
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requires_prefix=False,
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clobbers_flags=True,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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''')
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#
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# Compare and set flags.
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#
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@@ -40,6 +40,7 @@ use_lzcnt = And(has_lzcnt)
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# Presets corresponding to Intel CPUs.
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baseline = Preset(has_sse2)
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nehalem = Preset(
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has_sse2, has_sse3, has_ssse3, has_sse41, has_sse42, has_popcnt)
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haswell = Preset(nehalem, has_bmi1, has_lzcnt)
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