machinst x64: lower Ctz using the Bsf x86 instruction
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@@ -293,12 +293,15 @@ impl ToString for AluRmiROpcode {
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pub enum ReadOnlyGprRmROpcode {
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/// Bit-scan reverse.
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Bsr,
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/// Bit-scan forward.
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Bsf,
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}
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impl fmt::Debug for ReadOnlyGprRmROpcode {
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fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
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match self {
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ReadOnlyGprRmROpcode::Bsr => write!(fmt, "bsr"),
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ReadOnlyGprRmROpcode::Bsf => write!(fmt, "bsf"),
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}
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}
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}
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@@ -566,6 +566,7 @@ pub(crate) fn emit(
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let (opcode, num_opcodes) = match op {
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ReadOnlyGprRmROpcode::Bsr => (0x0fbd, 2),
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ReadOnlyGprRmROpcode::Bsf => (0x0fbc, 2),
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};
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match src {
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@@ -358,6 +358,38 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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));
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}
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Opcode::Ctz => {
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// TODO when the x86 flags have use_bmi1, we can use TZCNT.
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// General formula using bit-scan forward (BSF):
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// bsf %src, %dst
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// mov $(size_bits), %tmp
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// cmovz %tmp, %dst
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let ty = ctx.input_ty(insn, 0);
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let ty = if ty.bits() < 32 { I32 } else { ty };
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debug_assert!(ty == I32 || ty == I64);
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let src = input_to_reg_mem(ctx, inputs[0]);
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let dst = output_to_reg(ctx, outputs[0]);
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let tmp = ctx.alloc_tmp(RegClass::I64, ty);
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ctx.emit(Inst::imm_r(false /* 64 bits */, ty.bits() as u64, tmp));
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ctx.emit(Inst::read_only_gpr_rm_r(
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ty.bytes() as u8,
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ReadOnlyGprRmROpcode::Bsf,
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src,
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dst,
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));
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ctx.emit(Inst::cmove(
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ty.bytes() as u8,
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CC::Z,
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RegMem::reg(tmp.to_reg()),
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dst,
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));
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}
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Opcode::Uextend
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| Opcode::Sextend
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| Opcode::Bint
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