Add a RISC-V target.

Flesh out the directory structure for defining target instruction set
architectures. Use RISC-V as a startgin point because it is so simple.

meta/target/__init__.py

@@ -0,0 +1,16 @@
+"""
+Cretonne target definitions
+---------------------------
+
+The :py:mod:`target` package contains sub-packages for each target instruction
+set architecture supported by Cretonne.
+"""
+
+from . import riscv
+
+def all_targets():
+    """
+    Get a list of all the supported targets. Each target is represented as a
+    :py:class:`cretonne.Target` instance.
+    """
+    return [riscv.target]