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Update to rustfmt-preview (#348)

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* Update to rustfmt-preview.

* Run "cargo fmt --all" with rustfmt 0.4.1.

rustfmt 0.4.1 is the latest release of rustfmt-preview available on the
stable channel.

* Fix a long line that rustfmt 0.4.1 can't handle.

* Remove unneeded commas left behind by rustfmt.
This commit is contained in:
Dan Gohman
2018-05-25 11:38:38 -07:00
committed by GitHub
parent 99f6055c55
commit 6b88cd44a8
137 changed files with 1914 additions and 2380 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/codegen/src/isa/arm64/abi.rs
View File

@@ -17,7 +17,11 @@ pub fn legalize_signature(
/// Get register class for a type appearing in a legalized signature.
pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
if ty.is_int() { GPR } else { FPR }
if ty.is_int() {
GPR
} else {
FPR
}
}
/// Get the set of allocatable registers for `func`.

6
lib/codegen/src/isa/constraints.rs
View File

@@ -30,16 +30,14 @@ impl OperandConstraint {
/// counterpart operand has the same value location.
pub fn satisfied(&self, loc: ValueLoc) -> bool {
match self.kind {
ConstraintKind::Reg |
ConstraintKind::Tied(_) => {
ConstraintKind::Reg | ConstraintKind::Tied(_) => {
if let ValueLoc::Reg(reg) = loc {
self.regclass.contains(reg)
} else {
false
}
}
ConstraintKind::FixedReg(reg) |
ConstraintKind::FixedTied(reg) => {
ConstraintKind::FixedReg(reg) | ConstraintKind::FixedTied(reg) => {
loc == ValueLoc::Reg(reg) && self.regclass.contains(reg)
}
ConstraintKind::Stack => {

7
lib/codegen/src/isa/encoding.rs
View File

@@ -122,10 +122,9 @@ impl EncInfo {
///
/// Returns 0 for illegal encodings.
pub fn bytes(&self, enc: Encoding) -> CodeOffset {
self.sizing.get(enc.recipe()).map_or(
0,
|s| CodeOffset::from(s.bytes),
)
self.sizing
.get(enc.recipe())
.map_or(0, |s| CodeOffset::from(s.bytes))
}
/// Get the branch range that is supported by `enc`, if any.

7
lib/codegen/src/isa/mod.rs
View File

@@ -142,11 +142,8 @@ impl settings::Configurable for Builder {
/// legalize it?
///
/// The `Encodings` iterator returns a legalization function to call.
pub type Legalize = fn(ir::Inst,
&mut ir::Function,
&mut flowgraph::ControlFlowGraph,
&TargetIsa)
-> bool;
pub type Legalize =
fn(ir::Inst, &mut ir::Function, &mut flowgraph::ControlFlowGraph, &TargetIsa) -> bool;
/// Methods that are specialized to a target ISA. Implies a Display trait that shows the
/// shared flags, as well as any isa-specific flags.

10
lib/codegen/src/isa/registers.rs
View File

@@ -89,10 +89,12 @@ impl RegBank {
None
}
}
}.and_then(|offset| if offset < self.units {
Some(offset + self.first_unit)
} else {
None
}.and_then(|offset| {
if offset < self.units {
Some(offset + self.first_unit)
} else {
None
}
})
}

10
lib/codegen/src/isa/riscv/abi.rs
View File

@@ -117,17 +117,21 @@ pub fn legalize_signature(
/// Get register class for a type appearing in a legalized signature.
pub fn regclass_for_abi_type(ty: Type) -> RegClass {
if ty.is_float() { FPR } else { GPR }
if ty.is_float() {
FPR
} else {
GPR
}
}
pub fn allocatable_registers(_func: &ir::Function, isa_flags: &settings::Flags) -> RegisterSet {
let mut regs = RegisterSet::new();
regs.take(GPR, GPR.unit(0)); // Hard-wired 0.
// %x1 is the link register which is available for allocation.
// %x1 is the link register which is available for allocation.
regs.take(GPR, GPR.unit(2)); // Stack pointer.
regs.take(GPR, GPR.unit(3)); // Global pointer.
regs.take(GPR, GPR.unit(4)); // Thread pointer.
// TODO: %x8 is the frame pointer. Reserve it?
// TODO: %x8 is the frame pointer. Reserve it?
// Remove %x16 and up for RV32E.
if isa_flags.enable_e() {

6
lib/codegen/src/isa/stack.rs
View File

@@ -35,9 +35,9 @@ impl StackRef {
/// Get a reference to `ss` using the stack pointer as a base.
pub fn sp(ss: StackSlot, frame: &StackSlots) -> Self {
let size = frame.frame_size.expect(
"Stack layout must be computed before referencing stack slots",
);
let size = frame
.frame_size
.expect("Stack layout must be computed before referencing stack slots");
let slot = &frame[ss];
let offset = if slot.kind == StackSlotKind::OutgoingArg {
// Outgoing argument slots have offsets relative to our stack pointer.

25
lib/codegen/src/isa/x86/abi.rs
View File

@@ -6,8 +6,8 @@ use cursor::{Cursor, CursorPosition, EncCursor};
use ir;
use ir::immediates::Imm64;
use ir::stackslot::{StackOffset, StackSize};
use ir::{AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, InstBuilder, ValueLoc,
get_probestack_funcref};
use ir::{get_probestack_funcref, AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose,
InstBuilder, ValueLoc};
use isa::{RegClass, RegUnit, TargetIsa};
use regalloc::RegisterSet;
use result;
@@ -97,7 +97,8 @@ impl ArgAssigner for Args {
RU::r14
} else {
RU::rsi
} as RegUnit).into()
} as RegUnit)
.into()
}
// This is SpiderMonkey's `WasmTableCallSigReg`.
ArgumentPurpose::SignatureId => return ArgumentLoc::Reg(RU::rbx as RegUnit).into(),
@@ -235,8 +236,8 @@ fn callee_saved_gprs_used(flags: &shared_settings::Flags, func: &ir::Function) -
for ebb in &func.layout {
for inst in func.layout.ebb_insts(ebb) {
match func.dfg[inst] {
ir::instructions::InstructionData::RegMove { dst, .. } |
ir::instructions::InstructionData::RegFill { dst, .. } => {
ir::instructions::InstructionData::RegMove { dst, .. }
| ir::instructions::InstructionData::RegFill { dst, .. } => {
if !used.is_avail(GPR, dst) {
used.free(GPR, dst);
}
@@ -431,10 +432,8 @@ fn insert_common_prologue(
pos.func.locations[fp] = ir::ValueLoc::Reg(RU::rbp as RegUnit);
pos.ins().x86_push(fp);
pos.ins().copy_special(
RU::rsp as RegUnit,
RU::rbp as RegUnit,
);
pos.ins()
.copy_special(RU::rsp as RegUnit, RU::rbp as RegUnit);
for reg in csrs.iter(GPR) {
// Append param to entry EBB
@@ -449,8 +448,8 @@ fn insert_common_prologue(
// Allocate stack frame storage.
if stack_size > 0 {
if isa.flags().probestack_enabled() &&
stack_size > (1 << isa.flags().probestack_size_log2())
if isa.flags().probestack_enabled()
&& stack_size > (1 << isa.flags().probestack_size_log2())
{
// Emit a stack probe.
let rax = RU::rax as RegUnit;
@@ -464,8 +463,8 @@ fn insert_common_prologue(
let callee = get_probestack_funcref(pos.func, reg_type, rax, isa);
// Make the call.
let call = if !isa.flags().is_pic() && isa.flags().is_64bit() &&
!pos.func.dfg.ext_funcs[callee].colocated
let call = if !isa.flags().is_pic() && isa.flags().is_64bit()
&& !pos.func.dfg.ext_funcs[callee].colocated
{
// 64-bit non-PIC non-colocated calls need to be legalized to call_indirect.
// Use r11 as it may be clobbered under all supported calling conventions.

57
lib/codegen/src/isa/x86/enc_tables.rs
View File

@@ -84,11 +84,8 @@ fn expand_sdivrem(
// Explicitly check for overflow: Trap when x == INT_MIN.
debug_assert!(avoid_div_traps, "Native trapping divide handled above");
let f = pos.ins().ifcmp_imm(x, -1 << (ty.lane_bits() - 1));
pos.ins().trapif(
IntCC::Equal,
f,
ir::TrapCode::IntegerOverflow,
);
pos.ins()
.trapif(IntCC::Equal, f, ir::TrapCode::IntegerOverflow);
// x / -1 = -x.
pos.ins().irsub_imm(x, 0)
};
@@ -348,11 +345,8 @@ fn expand_fcvt_to_sint(
let mut pos = FuncCursor::new(func).after_inst(inst);
pos.use_srcloc(inst);
let is_done = pos.ins().icmp_imm(
IntCC::NotEqual,
result,
1 << (ty.lane_bits() - 1),
);
let is_done = pos.ins()
.icmp_imm(IntCC::NotEqual, result, 1 << (ty.lane_bits() - 1));
pos.ins().brnz(is_done, done, &[]);
// We now have the following possibilities:
@@ -364,10 +358,8 @@ fn expand_fcvt_to_sint(
// Check for NaN.
let is_nan = pos.ins().fcmp(FloatCC::Unordered, x, x);
pos.ins().trapnz(
is_nan,
ir::TrapCode::BadConversionToInteger,
);
pos.ins()
.trapnz(is_nan, ir::TrapCode::BadConversionToInteger);
// Check for case 1: INT_MIN is the correct result.
// Determine the smallest floating point number that would convert to INT_MIN.
@@ -376,14 +368,12 @@ fn expand_fcvt_to_sint(
let flimit = match xty {
// An f32 can represent `i16::min_value() - 1` exactly with precision to spare, so
// there are values less than -2^(N-1) that convert correctly to INT_MIN.
ir::types::F32 => {
pos.ins().f32const(if output_bits < 32 {
overflow_cc = FloatCC::LessThanOrEqual;
Ieee32::fcvt_to_sint_negative_overflow(output_bits)
} else {
Ieee32::pow2(output_bits - 1).neg()
})
}
ir::types::F32 => pos.ins().f32const(if output_bits < 32 {
overflow_cc = FloatCC::LessThanOrEqual;
Ieee32::fcvt_to_sint_negative_overflow(output_bits)
} else {
Ieee32::pow2(output_bits - 1).neg()
}),
ir::types::F64 => {
// An f64 can represent `i32::min_value() - 1` exactly with precision to spare, so
// there are values less than -2^(N-1) that convert correctly to INT_MIN.
@@ -458,12 +448,8 @@ fn expand_fcvt_to_uint(
_ => panic!("Can't convert {}", xty),
};
let is_large = pos.ins().ffcmp(x, pow2nm1);
pos.ins().brff(
FloatCC::GreaterThanOrEqual,
is_large,
large,
&[],
);
pos.ins()
.brff(FloatCC::GreaterThanOrEqual, is_large, large, &[]);
// We need to generate a specific trap code when `x` is NaN, so reuse the flags from the
// previous comparison.
@@ -476,12 +462,8 @@ fn expand_fcvt_to_uint(
// Now we know that x < 2^(N-1) and not NaN.
let sres = pos.ins().x86_cvtt2si(ty, x);
let is_neg = pos.ins().ifcmp_imm(sres, 0);
pos.ins().brif(
IntCC::SignedGreaterThanOrEqual,
is_neg,
done,
&[sres],
);
pos.ins()
.brif(IntCC::SignedGreaterThanOrEqual, is_neg, done, &[sres]);
pos.ins().trap(ir::TrapCode::IntegerOverflow);
// Handle the case where x >= 2^(N-1) and not NaN.
@@ -489,11 +471,8 @@ fn expand_fcvt_to_uint(
let adjx = pos.ins().fsub(x, pow2nm1);
let lres = pos.ins().x86_cvtt2si(ty, adjx);
let is_neg = pos.ins().ifcmp_imm(lres, 0);
pos.ins().trapif(
IntCC::SignedLessThan,
is_neg,
ir::TrapCode::IntegerOverflow,
);
pos.ins()
.trapif(IntCC::SignedLessThan, is_neg, ir::TrapCode::IntegerOverflow);
let lfinal = pos.ins().iadd_imm(lres, 1 << (ty.lane_bits() - 1));
// Recycle the original instruction as a jump.