Add Intel encodings for trapif.

This is implemented as a macro with a conditional jump over a ud2. This
way, we don't have to split up EBBs at every conditional trap.

lib/cretonne/meta/isa/intel/encodings.py

@@ -354,6 +354,10 @@ enc_both(base.brnz.b1, r.t8jccd_abcd, 0x85)
 I32.enc(base.trap, *r.trap(0x0f, 0x0b))
 I64.enc(base.trap, *r.trap(0x0f, 0x0b))
 
+# Using a standard EncRecipe, not the TailRecipe.
+I32.enc(base.trapif, r.trapif, 0)
+I64.enc(base.trapif, r.trapif, 0)
+
 #
 # Comparisons
 #

lib/cretonne/meta/isa/intel/recipes.py

@@ -8,7 +8,7 @@ from cdsl.registers import RegClass
 from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry, NullAry
 from base.formats import Trap, Call, IndirectCall, Store, Load
 from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
-from base.formats import IntSelect
+from base.formats import IntSelect, IntCondTrap
 from base.formats import Jump, Branch, BranchInt, BranchFloat
 from base.formats import Ternary, FuncAddr, UnaryGlobalVar
 from base.formats import RegMove, RegSpill, RegFill, CopySpecial
@@ -279,6 +279,19 @@ trap = TailRecipe(
         'trap', Trap, size=0, ins=(), outs=(),
         emit='PUT_OP(bits, BASE_REX, sink);')
 
+# Macro: conditional jump over a ud2.
+trapif = EncRecipe(
+        'trapif', IntCondTrap, size=4, ins=FLAG.eflags, outs=(),
+        clobbers_flags=False,
+        emit='''
+        // Jump over a 2-byte ud2.
+        sink.put1(0x70 | (icc2opc(cond.inverse()) as u8));
+        sink.put1(2);
+        // ud2.
+        sink.put1(0x0f);
+        sink.put1(0x0b);
+        ''')
+
 # XX /r
 rr = TailRecipe(
         'rr', Binary, size=1, ins=(GPR, GPR), outs=0,