diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index 02e7fc0364..5da0c709a6 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -512,5 +512,27 @@ ebb1:
     ; asm: setbe %bl
     [-,%rbx]            v29 = trueif ule v11                          ; bin: 0f 96 c3
 
+    ; The trapif instructions are encoded as macros: a conditional jump over a ud2.
+    ; asm: jne .+4; ud2
+    trapif eq v11, user0                           ; bin: 75 02 0f 0b
+    ; asm: je .+4; ud2
+    trapif ne v11, user0                           ; bin: 74 02 0f 0b
+    ; asm: jnl .+4; ud2
+    trapif slt v11, user0                          ; bin: 7d 02 0f 0b
+    ; asm: jnge .+4; ud2
+    trapif sge v11, user0                          ; bin: 7c 02 0f 0b
+    ; asm: jng .+4; ud2
+    trapif sgt v11, user0                          ; bin: 7e 02 0f 0b
+    ; asm: jnle .+4; ud2
+    trapif sle v11, user0                          ; bin: 7f 02 0f 0b
+    ; asm: jnb .+4; ud2
+    trapif ult v11, user0                          ; bin: 73 02 0f 0b
+    ; asm: jnae .+4; ud2
+    trapif uge v11, user0                          ; bin: 72 02 0f 0b
+    ; asm: jna .+4; ud2
+    trapif ugt v11, user0                          ; bin: 76 02 0f 0b
+    ; asm: jnbe .+4; ud2
+    trapif ule v11, user0                          ; bin: 77 02 0f 0b
+
     return
 }
diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton
index 719e6b1de5..29f75085d9 100644
--- a/cranelift/filetests/isa/intel/binary64.cton
+++ b/cranelift/filetests/isa/intel/binary64.cton
@@ -593,6 +593,28 @@ ebb1:
     ; asm: setbe %r11b
     [-,%r11]            v29 = trueif ule v11                          ; bin: 41 0f 96 c3
 
+    ; The trapif instructions are encoded as macros: a conditional jump over a ud2.
+    ; asm: jne .+4; ud2
+    trapif eq v11, user0                           ; bin: 75 02 0f 0b
+    ; asm: je .+4; ud2
+    trapif ne v11, user0                           ; bin: 74 02 0f 0b
+    ; asm: jnl .+4; ud2
+    trapif slt v11, user0                          ; bin: 7d 02 0f 0b
+    ; asm: jnge .+4; ud2
+    trapif sge v11, user0                          ; bin: 7c 02 0f 0b
+    ; asm: jng .+4; ud2
+    trapif sgt v11, user0                          ; bin: 7e 02 0f 0b
+    ; asm: jnle .+4; ud2
+    trapif sle v11, user0                          ; bin: 7f 02 0f 0b
+    ; asm: jnb .+4; ud2
+    trapif ult v11, user0                          ; bin: 73 02 0f 0b
+    ; asm: jnae .+4; ud2
+    trapif uge v11, user0                          ; bin: 72 02 0f 0b
+    ; asm: jna .+4; ud2
+    trapif ugt v11, user0                          ; bin: 76 02 0f 0b
+    ; asm: jnbe .+4; ud2
+    trapif ule v11, user0                          ; bin: 77 02 0f 0b
+
     return
 }
 
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index 0e962a66f1..5b9f8ae422 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -354,6 +354,10 @@ enc_both(base.brnz.b1, r.t8jccd_abcd, 0x85)
 I32.enc(base.trap, *r.trap(0x0f, 0x0b))
 I64.enc(base.trap, *r.trap(0x0f, 0x0b))
 
+# Using a standard EncRecipe, not the TailRecipe.
+I32.enc(base.trapif, r.trapif, 0)
+I64.enc(base.trapif, r.trapif, 0)
+
 #
 # Comparisons
 #
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 622430b9b2..7e74abae47 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -8,7 +8,7 @@ from cdsl.registers import RegClass
 from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry, NullAry
 from base.formats import Trap, Call, IndirectCall, Store, Load
 from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
-from base.formats import IntSelect
+from base.formats import IntSelect, IntCondTrap
 from base.formats import Jump, Branch, BranchInt, BranchFloat
 from base.formats import Ternary, FuncAddr, UnaryGlobalVar
 from base.formats import RegMove, RegSpill, RegFill, CopySpecial
@@ -279,6 +279,19 @@ trap = TailRecipe(
         'trap', Trap, size=0, ins=(), outs=(),
         emit='PUT_OP(bits, BASE_REX, sink);')
 
+# Macro: conditional jump over a ud2.
+trapif = EncRecipe(
+        'trapif', IntCondTrap, size=4, ins=FLAG.eflags, outs=(),
+        clobbers_flags=False,
+        emit='''
+        // Jump over a 2-byte ud2.
+        sink.put1(0x70 | (icc2opc(cond.inverse()) as u8));
+        sink.put1(2);
+        // ud2.
+        sink.put1(0x0f);
+        sink.put1(0x0b);
+        ''')
+
 # XX /r
 rr = TailRecipe(
         'rr', Binary, size=1, ins=(GPR, GPR), outs=0,
diff --git a/lib/cretonne/src/isa/intel/binemit.rs b/lib/cretonne/src/isa/intel/binemit.rs
index 0f07f049f3..2d045a0882 100644
--- a/lib/cretonne/src/isa/intel/binemit.rs
+++ b/lib/cretonne/src/isa/intel/binemit.rs
@@ -2,7 +2,7 @@
 
 use binemit::{CodeSink, Reloc, bad_encoding};
 use ir::{Function, Inst, Ebb, InstructionData, Opcode};
-use ir::condcodes::{IntCC, FloatCC};
+use ir::condcodes::{CondCode, IntCC, FloatCC};
 use isa::{RegUnit, StackRef, StackBase, StackBaseMask};
 use regalloc::RegDiversions;
 use super::registers::RU;