Optimize immediates and compare and branch sequences (#286)
* Add a pre-opt optimization to change constants into immediates. This converts 'iadd' + 'iconst' into 'iadd_imm', and so on. * Optimize away redundant `bint` instructions. Cretonne has a concept of "Testable" values, which can be either boolean or integer. When the an instruction needing a "Testable" value receives the result of a `bint`, converting boolean to integer, eliminate the `bint`, as it's redundant. * Postopt: Optimize using CPU flags. This introduces a post-legalization optimization pass which converts compare+branch sequences to use flags values on CPUs which support it. * Define a form of x86's `urm` that doesn't clobber FLAGS. movzbl/movsbl/etc. don't clobber FLAGS; define a form of the `urm` recipe that represents this. * Implement a DCE pass. This pass deletes instructions with no side effects and no results that are used. * Clarify ambiguity about "32-bit" and "64-bit" in comments. * Add x86 encodings for icmp_imm. * Add a testcase for postopt CPU flags optimization. This covers the basic functionality of transforming compare+branch sequences to use CPU flags. * Pattern-match irsub_imm in preopt.
This commit is contained in:
Dan Gohman
@@ -378,6 +378,8 @@ X86_64.enc(base.trapff, r.trapff, 0)
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# Comparisons
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#
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enc_i32_i64(base.icmp, r.icscc, 0x39)
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enc_i32_i64(base.icmp_imm, r.icsccib, 0x83, rrr=7)
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enc_i32_i64(base.icmp_imm, r.icsccid, 0x81, rrr=7)
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enc_i32_i64(base.ifcmp, r.rcmp, 0x39)
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enc_i32_i64(base.ifcmp_imm, r.rcmpib, 0x83, rrr=7)
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enc_i32_i64(base.ifcmp_imm, r.rcmpid, 0x81, rrr=7)
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@@ -409,11 +411,13 @@ enc_i32_i64(x86.bsr, r.bsf_and_bsr, 0x0F, 0xBD)
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#
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# This assumes that b1 is represented as an 8-bit low register with the value 0
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# or 1.
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X86_32.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
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X86_64.enc(base.bint.i64.b1, *r.urm.rex(0x0f, 0xb6)) # zext to i64 implicit.
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X86_64.enc(base.bint.i64.b1, *r.urm_abcd(0x0f, 0xb6)) # zext to i64 implicit.
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X86_64.enc(base.bint.i32.b1, *r.urm.rex(0x0f, 0xb6))
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X86_64.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
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#
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# Encode movzbq as movzbl, because it's equivalent and shorter.
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X86_32.enc(base.bint.i32.b1, *r.urm_noflags_abcd(0x0f, 0xb6))
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X86_64.enc(base.bint.i64.b1, *r.urm_noflags.rex(0x0f, 0xb6))
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X86_64.enc(base.bint.i64.b1, *r.urm_noflags_abcd(0x0f, 0xb6))
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X86_64.enc(base.bint.i32.b1, *r.urm_noflags.rex(0x0f, 0xb6))
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X86_64.enc(base.bint.i32.b1, *r.urm_noflags_abcd(0x0f, 0xb6))
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# Numerical conversions.
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@@ -430,41 +434,41 @@ X86_64.enc(base.ireduce.i32.i64, r.null, 0)
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# instructions for %al/%ax/%eax to %ax/%eax/%rax.
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# movsbl
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X86_32.enc(base.sextend.i32.i8, *r.urm(0x0f, 0xbe))
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X86_64.enc(base.sextend.i32.i8, *r.urm.rex(0x0f, 0xbe))
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X86_64.enc(base.sextend.i32.i8, *r.urm(0x0f, 0xbe))
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X86_32.enc(base.sextend.i32.i8, *r.urm_noflags(0x0f, 0xbe))
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X86_64.enc(base.sextend.i32.i8, *r.urm_noflags.rex(0x0f, 0xbe))
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X86_64.enc(base.sextend.i32.i8, *r.urm_noflags(0x0f, 0xbe))
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# movswl
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X86_32.enc(base.sextend.i32.i16, *r.urm(0x0f, 0xbf))
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X86_64.enc(base.sextend.i32.i16, *r.urm.rex(0x0f, 0xbf))
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X86_64.enc(base.sextend.i32.i16, *r.urm(0x0f, 0xbf))
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X86_32.enc(base.sextend.i32.i16, *r.urm_noflags(0x0f, 0xbf))
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X86_64.enc(base.sextend.i32.i16, *r.urm_noflags.rex(0x0f, 0xbf))
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X86_64.enc(base.sextend.i32.i16, *r.urm_noflags(0x0f, 0xbf))
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# movsbq
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X86_64.enc(base.sextend.i64.i8, *r.urm.rex(0x0f, 0xbe, w=1))
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X86_64.enc(base.sextend.i64.i8, *r.urm_noflags.rex(0x0f, 0xbe, w=1))
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# movswq
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X86_64.enc(base.sextend.i64.i16, *r.urm.rex(0x0f, 0xbf, w=1))
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X86_64.enc(base.sextend.i64.i16, *r.urm_noflags.rex(0x0f, 0xbf, w=1))
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# movslq
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X86_64.enc(base.sextend.i64.i32, *r.urm.rex(0x63, w=1))
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X86_64.enc(base.sextend.i64.i32, *r.urm_noflags.rex(0x63, w=1))
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# movzbl
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X86_32.enc(base.uextend.i32.i8, *r.urm(0x0f, 0xb6))
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X86_64.enc(base.uextend.i32.i8, *r.urm.rex(0x0f, 0xb6))
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X86_64.enc(base.uextend.i32.i8, *r.urm(0x0f, 0xb6))
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X86_32.enc(base.uextend.i32.i8, *r.urm_noflags(0x0f, 0xb6))
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X86_64.enc(base.uextend.i32.i8, *r.urm_noflags.rex(0x0f, 0xb6))
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X86_64.enc(base.uextend.i32.i8, *r.urm_noflags(0x0f, 0xb6))
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# movzwl
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X86_32.enc(base.uextend.i32.i16, *r.urm(0x0f, 0xb7))
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X86_64.enc(base.uextend.i32.i16, *r.urm.rex(0x0f, 0xb7))
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X86_64.enc(base.uextend.i32.i16, *r.urm(0x0f, 0xb7))
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X86_32.enc(base.uextend.i32.i16, *r.urm_noflags(0x0f, 0xb7))
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X86_64.enc(base.uextend.i32.i16, *r.urm_noflags.rex(0x0f, 0xb7))
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X86_64.enc(base.uextend.i32.i16, *r.urm_noflags(0x0f, 0xb7))
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# movzbq, encoded as movzbl because it's equivalent and shorter
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X86_64.enc(base.uextend.i64.i8, *r.urm.rex(0x0f, 0xb6))
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X86_64.enc(base.uextend.i64.i8, *r.urm(0x0f, 0xb6))
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X86_64.enc(base.uextend.i64.i8, *r.urm_noflags.rex(0x0f, 0xb6))
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X86_64.enc(base.uextend.i64.i8, *r.urm_noflags(0x0f, 0xb6))
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# movzwq, encoded as movzwl because it's equivalent and shorter
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X86_64.enc(base.uextend.i64.i16, *r.urm.rex(0x0f, 0xb7))
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X86_64.enc(base.uextend.i64.i16, *r.urm(0x0f, 0xb7))
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X86_64.enc(base.uextend.i64.i16, *r.urm_noflags.rex(0x0f, 0xb7))
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X86_64.enc(base.uextend.i64.i16, *r.urm_noflags(0x0f, 0xb7))
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# A 32-bit register copy clears the high 32 bits.
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X86_64.enc(base.uextend.i64.i32, *r.umr.rex(0x89))
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@@ -8,7 +8,8 @@ from cdsl.registers import RegClass
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from base.formats import Unary, UnaryImm, UnaryBool, Binary, BinaryImm
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from base.formats import MultiAry, NullAry
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from base.formats import Trap, Call, IndirectCall, Store, Load
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from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
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from base.formats import IntCompare, IntCompareImm, FloatCompare
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from base.formats import IntCond, FloatCond
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from base.formats import IntSelect, IntCondTrap, FloatCondTrap
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from base.formats import Jump, Branch, BranchInt, BranchFloat
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from base.formats import Ternary, FuncAddr, UnaryGlobalVar
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@@ -364,7 +365,7 @@ rfumr = TailRecipe(
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''')
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# XX /r, but for a unary operator with separate input/output register.
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# RM form.
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# RM form. Clobbers FLAGS.
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urm = TailRecipe(
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'urm', Unary, size=1, ins=GPR, outs=GPR,
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emit='''
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@@ -372,10 +373,19 @@ urm = TailRecipe(
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modrm_rr(in_reg0, out_reg0, sink);
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''')
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# XX /r. Same as urm, but input limited to ABCD.
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urm_abcd = TailRecipe(
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'urm_abcd', Unary, size=1, ins=ABCD, outs=GPR,
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when_prefixed=urm,
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# XX /r. Same as urm, but doesn't clobber FLAGS.
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urm_noflags = TailRecipe(
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'urm_noflags', Unary, size=1, ins=GPR, outs=GPR,
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clobbers_flags=False,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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''')
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# XX /r. Same as urm_noflags, but input limited to ABCD.
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urm_noflags_abcd = TailRecipe(
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'urm_noflags_abcd', Unary, size=1, ins=ABCD, outs=GPR,
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when_prefixed=urm_noflags,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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@@ -1360,6 +1370,61 @@ icscc = TailRecipe(
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modrm_rr(out_reg0, 0, sink);
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''')
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icsccib = TailRecipe(
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'icsccib', IntCompareImm, size=2 + 3, ins=GPR, outs=ABCD,
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instp=IsSignedInt(IntCompareImm.imm, 8),
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emit='''
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// Comparison instruction.
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PUT_OP(bits, rex1(in_reg0), sink);
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modrm_r_bits(in_reg0, bits, sink);
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let imm: i64 = imm.into();
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sink.put1(imm as u8);
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// `setCC` instruction, no REX.
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use ir::condcodes::IntCC::*;
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let setcc = match cond {
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Equal => 0x94,
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NotEqual => 0x95,
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SignedLessThan => 0x9c,
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SignedGreaterThanOrEqual => 0x9d,
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SignedGreaterThan => 0x9f,
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SignedLessThanOrEqual => 0x9e,
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UnsignedLessThan => 0x92,
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UnsignedGreaterThanOrEqual => 0x93,
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UnsignedGreaterThan => 0x97,
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UnsignedLessThanOrEqual => 0x96,
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};
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sink.put1(0x0f);
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sink.put1(setcc);
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modrm_rr(out_reg0, 0, sink);
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''')
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icsccid = TailRecipe(
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'icsccid', IntCompareImm, size=5 + 3, ins=GPR, outs=ABCD,
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instp=IsSignedInt(IntCompareImm.imm, 32),
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emit='''
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// Comparison instruction.
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PUT_OP(bits, rex1(in_reg0), sink);
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modrm_r_bits(in_reg0, bits, sink);
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let imm: i64 = imm.into();
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sink.put4(imm as u32);
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// `setCC` instruction, no REX.
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use ir::condcodes::IntCC::*;
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let setcc = match cond {
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Equal => 0x94,
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NotEqual => 0x95,
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SignedLessThan => 0x9c,
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SignedGreaterThanOrEqual => 0x9d,
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SignedGreaterThan => 0x9f,
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SignedLessThanOrEqual => 0x9e,
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UnsignedLessThan => 0x92,
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UnsignedGreaterThanOrEqual => 0x93,
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UnsignedGreaterThan => 0x97,
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UnsignedLessThanOrEqual => 0x96,
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};
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sink.put1(0x0f);
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sink.put1(setcc);
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modrm_rr(out_reg0, 0, sink);
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''')
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# Make a FloatCompare instruction predicate with the supported condition codes.
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