Optimize immediates and compare and branch sequences (#286)

* Add a pre-opt optimization to change constants into immediates.

This converts 'iadd' + 'iconst' into 'iadd_imm', and so on.

* Optimize away redundant `bint` instructions.

Cretonne has a concept of "Testable" values, which can be either boolean
or integer. When the an instruction needing a "Testable" value receives
the result of a `bint`, converting boolean to integer, eliminate the
`bint`, as it's redundant.

* Postopt: Optimize using CPU flags.

This introduces a post-legalization optimization pass which converts
compare+branch sequences to use flags values on CPUs which support it.

* Define a form of x86's `urm` that doesn't clobber FLAGS.

movzbl/movsbl/etc. don't clobber FLAGS; define a form of the `urm`
recipe that represents this.

* Implement a DCE pass.

This pass deletes instructions with no side effects and no results that
are used.

* Clarify ambiguity about "32-bit" and "64-bit" in comments.

* Add x86 encodings for icmp_imm.

* Add a testcase for postopt CPU flags optimization.

This covers the basic functionality of transforming compare+branch
sequences to use CPU flags.

* Pattern-match irsub_imm in preopt.

cranelift/filetests/dce/basic.cton

@@ -0,0 +1,46 @@
+test dce
+
+function %simple() -> i32 {
+ebb0:
+    v2 = iconst.i32 2
+    v3 = iconst.i32 3
+    return v3
+}
+; sameln: function %simple
+; nextln: ebb0:
+; nextln:     v3 = iconst.i32 3
+; nextln:     return v3
+; nextln: }
+
+function %some_branching(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+    v3 = iconst.i32 70
+    v4 = iconst.i32 71
+    v5 = iconst.i32 72
+    v8 = iconst.i32 73
+    brz v0, ebb1
+    jump ebb2(v8)
+
+ebb1:
+    v2 = iadd v0, v3
+    return v0
+
+ebb2(v9: i32):
+    v6 = iadd v1, v4
+    v7 = iadd v6, v9
+    return v7
+}
+; sameln: function %some_branching
+; nextln: ebb0(v0: i32, v1: i32):
+; nextln:     v4 = iconst.i32 71
+; nextln:     v8 = iconst.i32 73
+; nextln:     brz v0, ebb1
+; nextln:     jump ebb2(v8)
+; nextln: 
+; nextln: ebb1:
+; nextln:     return v0
+; nextln: 
+; nextln: ebb2(v9: i32):
+; nextln:     v6 = iadd.i32 v1, v4
+; nextln:     v7 = iadd v6, v9
+; nextln:     return v7