x64: Migrate {s,u}{div,rem} to ISLE (#6008)
* x64: Add precise-output tests for div traps
This adds a suite of `*.clif` files which are intended to test the
`avoid_div_traps=true` compilation of the `{s,u}{div,rem}` instructions.
* x64: Remove conditional regalloc in `Div` instruction
Move the 8-bit `Div` logic into a dedicated `Div8` instruction to avoid
having conditionally-used registers with respect to regalloc.
* x64: Migrate non-trapping, `udiv`/`urem` to ISLE
* x64: Port checked `udiv` to ISLE
* x64: Migrate urem entirely to ISLE
* x64: Use `test` instead of `cmp` to compare-to-zero
* x64: Port `sdiv` lowering to ISLE
* x64: Port `srem` lowering to ISLE
* Tidy up regalloc behavior and fix tests
* Update docs and winch
* Review comments
* Reword again
* More refactoring test fixes
* More test fixes
This commit is contained in:
Alex Crichton
@@ -5,10 +5,11 @@ use crate::{
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masm::{DivKind, OperandSize, RemKind},
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};
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use cranelift_codegen::{
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ir::TrapCode,
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isa::x64::{
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args::{
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self, AluRmiROpcode, Amode, DivOrRemKind, ExtMode, FromWritableReg, Gpr, GprMem,
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GprMemImm, RegMem, RegMemImm, SyntheticAmode, WritableGpr,
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self, AluRmiROpcode, Amode, CmpOpcode, DivSignedness, ExtMode, FromWritableReg, Gpr,
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GprMem, GprMemImm, RegMem, RegMemImm, SyntheticAmode, WritableGpr, CC,
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},
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settings as x64_settings, EmitInfo, EmitState, Inst,
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},
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@@ -64,20 +65,11 @@ impl From<OperandSize> for args::OperandSize {
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}
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}
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impl From<DivKind> for DivOrRemKind {
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fn from(kind: DivKind) -> Self {
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impl From<DivKind> for DivSignedness {
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fn from(kind: DivKind) -> DivSignedness {
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match kind {
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DivKind::Signed => DivOrRemKind::SignedDiv,
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DivKind::Unsigned => DivOrRemKind::UnsignedDiv,
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}
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}
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}
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impl From<RemKind> for DivOrRemKind {
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fn from(kind: RemKind) -> Self {
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match kind {
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RemKind::Signed => DivOrRemKind::SignedRem,
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RemKind::Unsigned => DivOrRemKind::UnsignedRem,
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DivKind::Signed => DivSignedness::Signed,
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DivKind::Unsigned => DivSignedness::Unsigned,
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}
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}
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}
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@@ -290,21 +282,61 @@ impl Assembler {
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/// caller has correctly allocated the dividend as `(rdx:rax)` and
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/// accounted for the quotient to be stored in `rax`.
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pub fn div(&mut self, divisor: Reg, dst: (Reg, Reg), kind: DivKind, size: OperandSize) {
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let tmp = if size == OperandSize::S64 && kind == DivKind::Signed {
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Some(regs::scratch())
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} else {
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None
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};
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match kind {
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// Signed division goes through a pseudo-instruction to validate
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// the divisor followed by a sign extension to initialize `rdx`.
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DivKind::Signed => {
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if size == OperandSize::S64 {
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self.emit(Inst::ValidateSdivDivisor64 {
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dividend: dst.0.into(),
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divisor: divisor.into(),
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tmp: regs::scratch().into(),
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});
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} else {
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self.emit(Inst::ValidateSdivDivisor {
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dividend: dst.0.into(),
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divisor: divisor.into(),
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size: size.into(),
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});
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}
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self.emit(Inst::SignExtendData {
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size: size.into(),
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src: dst.0.into(),
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dst: dst.1.into(),
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});
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}
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self.emit(Inst::CheckedDivOrRemSeq {
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kind: kind.into(),
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// Unsigned division only needs to check for 0 and then the `rdx`
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// divisor_hi is initialized with zero through an xor-against-itself
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// op.
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DivKind::Unsigned => {
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self.emit(Inst::CmpRmiR {
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size: size.into(),
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src: GprMemImm::new(RegMemImm::imm(0)).unwrap(),
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dst: divisor.into(),
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opcode: CmpOpcode::Cmp,
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});
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self.emit(Inst::TrapIf {
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cc: CC::Z,
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trap_code: TrapCode::IntegerDivisionByZero,
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});
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self.emit(Inst::AluRmiR {
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size: size.into(),
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op: AluRmiROpcode::Xor,
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src1: dst.1.into(),
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src2: dst.1.into(),
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dst: dst.1.into(),
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});
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}
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}
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self.emit(Inst::Div {
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sign: kind.into(),
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size: size.into(),
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divisor: divisor.into(),
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divisor: GprMem::new(RegMem::reg(divisor.into())).unwrap(),
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dividend_lo: dst.0.into(),
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dividend_hi: dst.1.into(),
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dst_quotient: dst.0.into(),
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dst_remainder: dst.1.into(),
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tmp: tmp.map(|reg| reg.into()),
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});
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}
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@@ -316,16 +348,58 @@ impl Assembler {
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/// caller has correctly allocated the dividend as `(rdx:rax)` and
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/// accounted for the remainder to be stored in `rdx`.
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pub fn rem(&mut self, divisor: Reg, dst: (Reg, Reg), kind: RemKind, size: OperandSize) {
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self.emit(Inst::CheckedDivOrRemSeq {
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kind: kind.into(),
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// First check for zero and explicitly trap.
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self.emit(Inst::CmpRmiR {
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size: size.into(),
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divisor: divisor.into(),
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dividend_lo: dst.0.into(),
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dividend_hi: dst.1.into(),
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dst_quotient: dst.0.into(),
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dst_remainder: dst.1.into(),
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tmp: None,
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src: GprMemImm::new(RegMemImm::imm(0)).unwrap(),
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dst: divisor.into(),
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opcode: CmpOpcode::Cmp,
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});
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self.emit(Inst::TrapIf {
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cc: CC::Z,
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trap_code: TrapCode::IntegerDivisionByZero,
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});
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match kind {
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// Signed remainder goes through a pseudo-instruction which has
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// some internal branching. The `dividend_hi`, or `rdx`, is
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// initialized here with a `SignExtendData` instruction.
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RemKind::Signed => {
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self.emit(Inst::SignExtendData {
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size: size.into(),
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src: dst.0.into(),
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dst: dst.1.into(),
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});
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self.emit(Inst::CheckedSRemSeq {
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size: size.into(),
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divisor: divisor.into(),
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dividend_lo: dst.0.into(),
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dividend_hi: dst.1.into(),
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dst_quotient: dst.0.into(),
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dst_remainder: dst.1.into(),
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});
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}
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// Unsigned remainder initializes `dividend_hi` with zero and
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// then executes a normal `div` instruction.
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RemKind::Unsigned => {
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self.emit(Inst::AluRmiR {
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size: size.into(),
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op: AluRmiROpcode::Xor,
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src1: dst.1.into(),
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src2: dst.1.into(),
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dst: dst.1.into(),
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});
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self.emit(Inst::Div {
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sign: DivSignedness::Unsigned,
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size: size.into(),
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divisor: GprMem::new(RegMem::reg(divisor.into())).unwrap(),
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dividend_lo: dst.0.into(),
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dividend_hi: dst.1.into(),
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dst_quotient: dst.0.into(),
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dst_remainder: dst.1.into(),
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});
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}
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}
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}
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/// Multiply immediate and register.
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@@ -14,7 +14,7 @@
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;; e: 83f900 cmp ecx, 0
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;; 11: 0f8502000000 jne 0x19
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;; 17: 0f0b ud2
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;; 19: ba00000000 mov edx, 0
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;; 1e: f7f1 div ecx
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;; 20: 5d pop rbp
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;; 21: c3 ret
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;; 19: 31d2 xor edx, edx
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;; 1b: f7f1 div ecx
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;; 1d: 5d pop rbp
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;; 1e: c3 ret
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@@ -14,7 +14,7 @@
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;; e: 83f900 cmp ecx, 0
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;; 11: 0f8502000000 jne 0x19
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;; 17: 0f0b ud2
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;; 19: ba00000000 mov edx, 0
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;; 1e: f7f1 div ecx
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;; 20: 5d pop rbp
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;; 21: c3 ret
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;; 19: 31d2 xor edx, edx
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;; 1b: f7f1 div ecx
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;; 1d: 5d pop rbp
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;; 1e: c3 ret
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@@ -17,8 +17,8 @@
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;; 16: 83f900 cmp ecx, 0
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;; 19: 0f8502000000 jne 0x21
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;; 1f: 0f0b ud2
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;; 21: ba00000000 mov edx, 0
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;; 26: f7f1 div ecx
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;; 28: 4883c408 add rsp, 8
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;; 2c: 5d pop rbp
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;; 2d: c3 ret
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;; 21: 31d2 xor edx, edx
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;; 23: f7f1 div ecx
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;; 25: 4883c408 add rsp, 8
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;; 29: 5d pop rbp
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;; 2a: c3 ret
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@@ -14,7 +14,7 @@
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;; e: 83f900 cmp ecx, 0
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;; 11: 0f8502000000 jne 0x19
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;; 17: 0f0b ud2
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;; 19: ba00000000 mov edx, 0
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;; 1e: f7f1 div ecx
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;; 20: 5d pop rbp
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;; 21: c3 ret
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;; 19: 31d2 xor edx, edx
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;; 1b: f7f1 div ecx
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;; 1d: 5d pop rbp
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;; 1e: c3 ret
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@@ -14,7 +14,7 @@
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;; e: 83f900 cmp ecx, 0
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;; 11: 0f8502000000 jne 0x19
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;; 17: 0f0b ud2
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;; 19: ba00000000 mov edx, 0
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;; 1e: f7f1 div ecx
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;; 20: 5d pop rbp
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;; 21: c3 ret
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;; 19: 31d2 xor edx, edx
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;; 1b: f7f1 div ecx
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;; 1d: 5d pop rbp
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;; 1e: c3 ret
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@@ -14,11 +14,11 @@
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;; e: 83f900 cmp ecx, 0
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;; 11: 0f8502000000 jne 0x19
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;; 17: 0f0b ud2
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;; 19: 83f9ff cmp ecx, -1
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;; 1c: 0f850a000000 jne 0x2c
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;; 22: b800000000 mov eax, 0
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;; 27: e903000000 jmp 0x2f
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;; 2c: 99 cdq
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;; 19: 99 cdq
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;; 1a: 83f9ff cmp ecx, -1
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;; 1d: 0f850a000000 jne 0x2d
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;; 23: ba00000000 mov edx, 0
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;; 28: e902000000 jmp 0x2f
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;; 2d: f7f9 idiv ecx
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;; 2f: 4889d0 mov rax, rdx
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;; 32: 5d pop rbp
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@@ -14,11 +14,11 @@
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;; e: 83f900 cmp ecx, 0
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;; 11: 0f8502000000 jne 0x19
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;; 17: 0f0b ud2
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;; 19: 83f9ff cmp ecx, -1
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;; 1c: 0f850a000000 jne 0x2c
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;; 22: b800000000 mov eax, 0
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;; 27: e903000000 jmp 0x2f
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;; 2c: 99 cdq
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;; 19: 99 cdq
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;; 1a: 83f9ff cmp ecx, -1
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;; 1d: 0f850a000000 jne 0x2d
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;; 23: ba00000000 mov edx, 0
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;; 28: e902000000 jmp 0x2f
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;; 2d: f7f9 idiv ecx
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;; 2f: 4889d0 mov rax, rdx
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;; 32: 5d pop rbp
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@@ -14,11 +14,11 @@
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;; e: 83f900 cmp ecx, 0
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;; 11: 0f8502000000 jne 0x19
|
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;; 17: 0f0b ud2
|
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;; 19: 83f9ff cmp ecx, -1
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;; 1c: 0f850a000000 jne 0x2c
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;; 22: b800000000 mov eax, 0
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;; 27: e903000000 jmp 0x2f
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;; 2c: 99 cdq
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;; 19: 99 cdq
|
||||
;; 1a: 83f9ff cmp ecx, -1
|
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;; 1d: 0f850a000000 jne 0x2d
|
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;; 23: ba00000000 mov edx, 0
|
||||
;; 28: e902000000 jmp 0x2f
|
||||
;; 2d: f7f9 idiv ecx
|
||||
;; 2f: 4889d0 mov rax, rdx
|
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;; 32: 5d pop rbp
|
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|
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@@ -17,11 +17,11 @@
|
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;; 16: 83f900 cmp ecx, 0
|
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;; 19: 0f8502000000 jne 0x21
|
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;; 1f: 0f0b ud2
|
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;; 21: 83f9ff cmp ecx, -1
|
||||
;; 24: 0f850a000000 jne 0x34
|
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;; 2a: b800000000 mov eax, 0
|
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;; 2f: e903000000 jmp 0x37
|
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;; 34: 99 cdq
|
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;; 21: 99 cdq
|
||||
;; 22: 83f9ff cmp ecx, -1
|
||||
;; 25: 0f850a000000 jne 0x35
|
||||
;; 2b: ba00000000 mov edx, 0
|
||||
;; 30: e902000000 jmp 0x37
|
||||
;; 35: f7f9 idiv ecx
|
||||
;; 37: 4889d0 mov rax, rdx
|
||||
;; 3a: 4883c408 add rsp, 8
|
||||
|
||||
@@ -14,11 +14,11 @@
|
||||
;; e: 83f900 cmp ecx, 0
|
||||
;; 11: 0f8502000000 jne 0x19
|
||||
;; 17: 0f0b ud2
|
||||
;; 19: 83f9ff cmp ecx, -1
|
||||
;; 1c: 0f850a000000 jne 0x2c
|
||||
;; 22: b800000000 mov eax, 0
|
||||
;; 27: e903000000 jmp 0x2f
|
||||
;; 2c: 99 cdq
|
||||
;; 19: 99 cdq
|
||||
;; 1a: 83f9ff cmp ecx, -1
|
||||
;; 1d: 0f850a000000 jne 0x2d
|
||||
;; 23: ba00000000 mov edx, 0
|
||||
;; 28: e902000000 jmp 0x2f
|
||||
;; 2d: f7f9 idiv ecx
|
||||
;; 2f: 4889d0 mov rax, rdx
|
||||
;; 32: 5d pop rbp
|
||||
|
||||
@@ -14,8 +14,8 @@
|
||||
;; e: 83f900 cmp ecx, 0
|
||||
;; 11: 0f8502000000 jne 0x19
|
||||
;; 17: 0f0b ud2
|
||||
;; 19: ba00000000 mov edx, 0
|
||||
;; 1e: f7f1 div ecx
|
||||
;; 20: 4889d0 mov rax, rdx
|
||||
;; 23: 5d pop rbp
|
||||
;; 24: c3 ret
|
||||
;; 19: 31d2 xor edx, edx
|
||||
;; 1b: f7f1 div ecx
|
||||
;; 1d: 4889d0 mov rax, rdx
|
||||
;; 20: 5d pop rbp
|
||||
;; 21: c3 ret
|
||||
|
||||
@@ -14,8 +14,8 @@
|
||||
;; e: 83f900 cmp ecx, 0
|
||||
;; 11: 0f8502000000 jne 0x19
|
||||
;; 17: 0f0b ud2
|
||||
;; 19: ba00000000 mov edx, 0
|
||||
;; 1e: f7f1 div ecx
|
||||
;; 20: 4889d0 mov rax, rdx
|
||||
;; 23: 5d pop rbp
|
||||
;; 24: c3 ret
|
||||
;; 19: 31d2 xor edx, edx
|
||||
;; 1b: f7f1 div ecx
|
||||
;; 1d: 4889d0 mov rax, rdx
|
||||
;; 20: 5d pop rbp
|
||||
;; 21: c3 ret
|
||||
|
||||
@@ -17,9 +17,9 @@
|
||||
;; 16: 83f900 cmp ecx, 0
|
||||
;; 19: 0f8502000000 jne 0x21
|
||||
;; 1f: 0f0b ud2
|
||||
;; 21: ba00000000 mov edx, 0
|
||||
;; 26: f7f1 div ecx
|
||||
;; 28: 4889d0 mov rax, rdx
|
||||
;; 2b: 4883c408 add rsp, 8
|
||||
;; 2f: 5d pop rbp
|
||||
;; 30: c3 ret
|
||||
;; 21: 31d2 xor edx, edx
|
||||
;; 23: f7f1 div ecx
|
||||
;; 25: 4889d0 mov rax, rdx
|
||||
;; 28: 4883c408 add rsp, 8
|
||||
;; 2c: 5d pop rbp
|
||||
;; 2d: c3 ret
|
||||
|
||||
@@ -14,8 +14,8 @@
|
||||
;; e: 83f900 cmp ecx, 0
|
||||
;; 11: 0f8502000000 jne 0x19
|
||||
;; 17: 0f0b ud2
|
||||
;; 19: ba00000000 mov edx, 0
|
||||
;; 1e: f7f1 div ecx
|
||||
;; 20: 4889d0 mov rax, rdx
|
||||
;; 23: 5d pop rbp
|
||||
;; 24: c3 ret
|
||||
;; 19: 31d2 xor edx, edx
|
||||
;; 1b: f7f1 div ecx
|
||||
;; 1d: 4889d0 mov rax, rdx
|
||||
;; 20: 5d pop rbp
|
||||
;; 21: c3 ret
|
||||
|
||||
@@ -14,8 +14,8 @@
|
||||
;; e: 83f900 cmp ecx, 0
|
||||
;; 11: 0f8502000000 jne 0x19
|
||||
;; 17: 0f0b ud2
|
||||
;; 19: ba00000000 mov edx, 0
|
||||
;; 1e: f7f1 div ecx
|
||||
;; 20: 4889d0 mov rax, rdx
|
||||
;; 23: 5d pop rbp
|
||||
;; 24: c3 ret
|
||||
;; 19: 31d2 xor edx, edx
|
||||
;; 1b: f7f1 div ecx
|
||||
;; 1d: 4889d0 mov rax, rdx
|
||||
;; 20: 5d pop rbp
|
||||
;; 21: c3 ret
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: ba00000000 mov edx, 0
|
||||
;; 23: 48f7f1 div rcx
|
||||
;; 26: 5d pop rbp
|
||||
;; 27: c3 ret
|
||||
;; 1e: 4831d2 xor rdx, rdx
|
||||
;; 21: 48f7f1 div rcx
|
||||
;; 24: 5d pop rbp
|
||||
;; 25: c3 ret
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: ba00000000 mov edx, 0
|
||||
;; 23: 48f7f1 div rcx
|
||||
;; 26: 5d pop rbp
|
||||
;; 27: c3 ret
|
||||
;; 1e: 4831d2 xor rdx, rdx
|
||||
;; 21: 48f7f1 div rcx
|
||||
;; 24: 5d pop rbp
|
||||
;; 25: c3 ret
|
||||
|
||||
@@ -17,8 +17,8 @@
|
||||
;; 1a: 4883f900 cmp rcx, 0
|
||||
;; 1e: 0f8502000000 jne 0x26
|
||||
;; 24: 0f0b ud2
|
||||
;; 26: ba00000000 mov edx, 0
|
||||
;; 2b: 48f7f1 div rcx
|
||||
;; 2e: 4883c410 add rsp, 0x10
|
||||
;; 32: 5d pop rbp
|
||||
;; 33: c3 ret
|
||||
;; 26: 4831d2 xor rdx, rdx
|
||||
;; 29: 48f7f1 div rcx
|
||||
;; 2c: 4883c410 add rsp, 0x10
|
||||
;; 30: 5d pop rbp
|
||||
;; 31: c3 ret
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: ba00000000 mov edx, 0
|
||||
;; 23: 48f7f1 div rcx
|
||||
;; 26: 5d pop rbp
|
||||
;; 27: c3 ret
|
||||
;; 1e: 4831d2 xor rdx, rdx
|
||||
;; 21: 48f7f1 div rcx
|
||||
;; 24: 5d pop rbp
|
||||
;; 25: c3 ret
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: ba00000000 mov edx, 0
|
||||
;; 23: 48f7f1 div rcx
|
||||
;; 26: 5d pop rbp
|
||||
;; 27: c3 ret
|
||||
;; 1e: 4831d2 xor rdx, rdx
|
||||
;; 21: 48f7f1 div rcx
|
||||
;; 24: 5d pop rbp
|
||||
;; 25: c3 ret
|
||||
|
||||
@@ -14,11 +14,11 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: 4883f9ff cmp rcx, -1
|
||||
;; 22: 0f850a000000 jne 0x32
|
||||
;; 28: b800000000 mov eax, 0
|
||||
;; 2d: e905000000 jmp 0x37
|
||||
;; 32: 4899 cqo
|
||||
;; 1e: 4899 cqo
|
||||
;; 20: 4883f9ff cmp rcx, -1
|
||||
;; 24: 0f850a000000 jne 0x34
|
||||
;; 2a: ba00000000 mov edx, 0
|
||||
;; 2f: e903000000 jmp 0x37
|
||||
;; 34: 48f7f9 idiv rcx
|
||||
;; 37: 4889d0 mov rax, rdx
|
||||
;; 3a: 5d pop rbp
|
||||
|
||||
@@ -14,11 +14,11 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: 4883f9ff cmp rcx, -1
|
||||
;; 22: 0f850a000000 jne 0x32
|
||||
;; 28: b800000000 mov eax, 0
|
||||
;; 2d: e905000000 jmp 0x37
|
||||
;; 32: 4899 cqo
|
||||
;; 1e: 4899 cqo
|
||||
;; 20: 4883f9ff cmp rcx, -1
|
||||
;; 24: 0f850a000000 jne 0x34
|
||||
;; 2a: ba00000000 mov edx, 0
|
||||
;; 2f: e903000000 jmp 0x37
|
||||
;; 34: 48f7f9 idiv rcx
|
||||
;; 37: 4889d0 mov rax, rdx
|
||||
;; 3a: 5d pop rbp
|
||||
|
||||
@@ -15,11 +15,11 @@
|
||||
;; 15: 4883f900 cmp rcx, 0
|
||||
;; 19: 0f8502000000 jne 0x21
|
||||
;; 1f: 0f0b ud2
|
||||
;; 21: 4883f9ff cmp rcx, -1
|
||||
;; 25: 0f850a000000 jne 0x35
|
||||
;; 2b: b800000000 mov eax, 0
|
||||
;; 30: e905000000 jmp 0x3a
|
||||
;; 35: 4899 cqo
|
||||
;; 21: 4899 cqo
|
||||
;; 23: 4883f9ff cmp rcx, -1
|
||||
;; 27: 0f850a000000 jne 0x37
|
||||
;; 2d: ba00000000 mov edx, 0
|
||||
;; 32: e903000000 jmp 0x3a
|
||||
;; 37: 48f7f9 idiv rcx
|
||||
;; 3a: 4889d0 mov rax, rdx
|
||||
;; 3d: 5d pop rbp
|
||||
|
||||
@@ -17,11 +17,11 @@
|
||||
;; 1a: 4883f900 cmp rcx, 0
|
||||
;; 1e: 0f8502000000 jne 0x26
|
||||
;; 24: 0f0b ud2
|
||||
;; 26: 4883f9ff cmp rcx, -1
|
||||
;; 2a: 0f850a000000 jne 0x3a
|
||||
;; 30: b800000000 mov eax, 0
|
||||
;; 35: e905000000 jmp 0x3f
|
||||
;; 3a: 4899 cqo
|
||||
;; 26: 4899 cqo
|
||||
;; 28: 4883f9ff cmp rcx, -1
|
||||
;; 2c: 0f850a000000 jne 0x3c
|
||||
;; 32: ba00000000 mov edx, 0
|
||||
;; 37: e903000000 jmp 0x3f
|
||||
;; 3c: 48f7f9 idiv rcx
|
||||
;; 3f: 4889d0 mov rax, rdx
|
||||
;; 42: 4883c410 add rsp, 0x10
|
||||
|
||||
@@ -14,11 +14,11 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: 4883f9ff cmp rcx, -1
|
||||
;; 22: 0f850a000000 jne 0x32
|
||||
;; 28: b800000000 mov eax, 0
|
||||
;; 2d: e905000000 jmp 0x37
|
||||
;; 32: 4899 cqo
|
||||
;; 1e: 4899 cqo
|
||||
;; 20: 4883f9ff cmp rcx, -1
|
||||
;; 24: 0f850a000000 jne 0x34
|
||||
;; 2a: ba00000000 mov edx, 0
|
||||
;; 2f: e903000000 jmp 0x37
|
||||
;; 34: 48f7f9 idiv rcx
|
||||
;; 37: 4889d0 mov rax, rdx
|
||||
;; 3a: 5d pop rbp
|
||||
|
||||
@@ -14,8 +14,8 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: ba00000000 mov edx, 0
|
||||
;; 23: 48f7f1 div rcx
|
||||
;; 26: 4889d0 mov rax, rdx
|
||||
;; 29: 5d pop rbp
|
||||
;; 2a: c3 ret
|
||||
;; 1e: 4831d2 xor rdx, rdx
|
||||
;; 21: 48f7f1 div rcx
|
||||
;; 24: 4889d0 mov rax, rdx
|
||||
;; 27: 5d pop rbp
|
||||
;; 28: c3 ret
|
||||
|
||||
@@ -14,8 +14,8 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: ba00000000 mov edx, 0
|
||||
;; 23: 48f7f1 div rcx
|
||||
;; 26: 4889d0 mov rax, rdx
|
||||
;; 29: 5d pop rbp
|
||||
;; 2a: c3 ret
|
||||
;; 1e: 4831d2 xor rdx, rdx
|
||||
;; 21: 48f7f1 div rcx
|
||||
;; 24: 4889d0 mov rax, rdx
|
||||
;; 27: 5d pop rbp
|
||||
;; 28: c3 ret
|
||||
|
||||
@@ -17,9 +17,9 @@
|
||||
;; 1a: 4883f900 cmp rcx, 0
|
||||
;; 1e: 0f8502000000 jne 0x26
|
||||
;; 24: 0f0b ud2
|
||||
;; 26: ba00000000 mov edx, 0
|
||||
;; 2b: 48f7f1 div rcx
|
||||
;; 2e: 4889d0 mov rax, rdx
|
||||
;; 31: 4883c410 add rsp, 0x10
|
||||
;; 35: 5d pop rbp
|
||||
;; 36: c3 ret
|
||||
;; 26: 4831d2 xor rdx, rdx
|
||||
;; 29: 48f7f1 div rcx
|
||||
;; 2c: 4889d0 mov rax, rdx
|
||||
;; 2f: 4883c410 add rsp, 0x10
|
||||
;; 33: 5d pop rbp
|
||||
;; 34: c3 ret
|
||||
|
||||
@@ -14,8 +14,8 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: ba00000000 mov edx, 0
|
||||
;; 23: 48f7f1 div rcx
|
||||
;; 26: 4889d0 mov rax, rdx
|
||||
;; 29: 5d pop rbp
|
||||
;; 2a: c3 ret
|
||||
;; 1e: 4831d2 xor rdx, rdx
|
||||
;; 21: 48f7f1 div rcx
|
||||
;; 24: 4889d0 mov rax, rdx
|
||||
;; 27: 5d pop rbp
|
||||
;; 28: c3 ret
|
||||
|
||||
@@ -14,8 +14,8 @@
|
||||
;; 12: 4883f900 cmp rcx, 0
|
||||
;; 16: 0f8502000000 jne 0x1e
|
||||
;; 1c: 0f0b ud2
|
||||
;; 1e: ba00000000 mov edx, 0
|
||||
;; 23: 48f7f1 div rcx
|
||||
;; 26: 4889d0 mov rax, rdx
|
||||
;; 29: 5d pop rbp
|
||||
;; 2a: c3 ret
|
||||
;; 1e: 4831d2 xor rdx, rdx
|
||||
;; 21: 48f7f1 div rcx
|
||||
;; 24: 4889d0 mov rax, rdx
|
||||
;; 27: 5d pop rbp
|
||||
;; 28: c3 ret
|
||||
|
||||
Reference in New Issue
Block a user