x64: Migrate {s,u}{div,rem} to ISLE (#6008)

* x64: Add precise-output tests for div traps

This adds a suite of `*.clif` files which are intended to test the
`avoid_div_traps=true` compilation of the `{s,u}{div,rem}` instructions.

* x64: Remove conditional regalloc in `Div` instruction

Move the 8-bit `Div` logic into a dedicated `Div8` instruction to avoid
having conditionally-used registers with respect to regalloc.

* x64: Migrate non-trapping, `udiv`/`urem` to ISLE

* x64: Port checked `udiv` to ISLE

* x64: Migrate urem entirely to ISLE

* x64: Use `test` instead of `cmp` to compare-to-zero

* x64: Port `sdiv` lowering to ISLE

* x64: Port `srem` lowering to ISLE

* Tidy up regalloc behavior and fix tests

* Update docs and winch

* Review comments

* Reword again

* More refactoring test fixes

* More test fixes

cranelift/filetests/filetests/isa/x64/sdiv-checked.clif

@@ -0,0 +1,285 @@
+test compile precise-output
+set avoid_div_traps=true
+target x86_64
+
+function %f1(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = sdiv v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movq    %rdi, %rax
+;   cbw %al, %al
+;   validate_sdiv_divisor %sil, %al
+;   idiv    %al, %sil, %al
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movq %rdi, %rax
+;   cbtw
+;   cmpb $0, %sil
+;   jne 0x15
+;   ud2 ; trap: int_divz
+;   cmpb $0xff, %sil
+;   jne 0x2a
+;   cmpb $0x80, %al
+;   jne 0x2a
+;   ud2 ; trap: int_ovf
+;   idivb %sil ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %f2(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = sdiv v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   validate_sdiv_divisor %si, %di
+;   movq    %rdi, %rax
+;   cwd %ax, %dx
+;   idiv    %ax, %dx, %si, %ax, %dx
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   cmpw $0, %si
+;   jne 0x10
+;   ud2 ; trap: int_divz
+;   cmpw $-1, %si
+;   jne 0x27
+;   cmpw $0x8000, %di
+;   jne 0x27
+;   ud2 ; trap: int_ovf
+;   movq %rdi, %rax
+;   cwtd
+;   idivw %si ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %f3(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = sdiv v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   validate_sdiv_divisor %esi, %edi
+;   movq    %rdi, %rax
+;   cdq %eax, %edx
+;   idiv    %eax, %edx, %esi, %eax, %edx
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   cmpl $0, %esi
+;   jne 0xf
+;   ud2 ; trap: int_divz
+;   cmpl $-1, %esi
+;   jne 0x26
+;   cmpl $0x80000000, %edi
+;   jne 0x26
+;   ud2 ; trap: int_ovf
+;   movq %rdi, %rax
+;   cltd
+;   idivl %esi ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %f4(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = sdiv v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   validate_sdiv_divisor %rsi, %rdi %rcx
+;   movq    %rdi, %rax
+;   cqo %rax, %rdx
+;   idiv    %rax, %rdx, %rsi, %rax, %rdx
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   cmpq $0, %rsi
+;   jne 0x10
+;   ud2 ; trap: int_divz
+;   cmpq $-1, %rsi
+;   jne 0x2f
+;   movabsq $9223372036854775808, %rcx
+;   cmpq %rcx, %rdi
+;   jne 0x2f
+;   ud2 ; trap: int_ovf
+;   movq %rdi, %rax
+;   cqto
+;   idivq %rsi ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %i8_imm(i8) -> i8 {
+block0(v0: i8):
+  v1 = iconst.i8 17
+  v2 = sdiv v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movq    %rdi, %rax
+;   cbw %al, %al
+;   movl    $17, %edx
+;   idiv    %al, %dl, %al
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movq %rdi, %rax
+;   cbtw
+;   movl $0x11, %edx
+;   idivb %dl ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %i16_imm(i16) -> i16 {
+block0(v0: i16):
+  v1 = iconst.i16 17
+  v2 = sdiv v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movl    $17, %ecx
+;   movq    %rdi, %rax
+;   cwd %ax, %dx
+;   idiv    %ax, %dx, %cx, %ax, %dx
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movl $0x11, %ecx
+;   movq %rdi, %rax
+;   cwtd
+;   idivw %cx ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %i32_imm(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 17
+  v2 = sdiv v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movl    $17, %ecx
+;   movq    %rdi, %rax
+;   cdq %eax, %edx
+;   idiv    %eax, %edx, %ecx, %eax, %edx
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movl $0x11, %ecx
+;   movq %rdi, %rax
+;   cltd
+;   idivl %ecx ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+
+function %i64_imm(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i64 17
+  v2 = sdiv v0, v1
+  return v2
+}
+
+; VCode:
+;   pushq   %rbp
+;   movq    %rsp, %rbp
+; block0:
+;   movl    $17, %ecx
+;   movq    %rdi, %rax
+;   cqo %rax, %rdx
+;   idiv    %rax, %rdx, %rcx, %rax, %rdx
+;   movq    %rbp, %rsp
+;   popq    %rbp
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   pushq %rbp
+;   movq %rsp, %rbp
+; block1: ; offset 0x4
+;   movl $0x11, %ecx
+;   movq %rdi, %rax
+;   cqto
+;   idivq %rcx ; trap: int_divz
+;   movq %rbp, %rsp
+;   popq %rbp
+;   retq
+