5c1b468648
* x64: Add precise-output tests for div traps
This adds a suite of `*.clif` files which are intended to test the
`avoid_div_traps=true` compilation of the `{s,u}{div,rem}` instructions.
* x64: Remove conditional regalloc in `Div` instruction
Move the 8-bit `Div` logic into a dedicated `Div8` instruction to avoid
having conditionally-used registers with respect to regalloc.
* x64: Migrate non-trapping, `udiv`/`urem` to ISLE
* x64: Port checked `udiv` to ISLE
* x64: Migrate urem entirely to ISLE
* x64: Use `test` instead of `cmp` to compare-to-zero
* x64: Port `sdiv` lowering to ISLE
* x64: Port `srem` lowering to ISLE
* Tidy up regalloc behavior and fix tests
* Update docs and winch
* Review comments
* Reword again
* More refactoring test fixes
* More test fixes
286 lines
4.8 KiB
Plaintext
286 lines
4.8 KiB
Plaintext
test compile precise-output
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set avoid_div_traps=true
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target x86_64
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function %f1(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = sdiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cbw %al, %al
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; validate_sdiv_divisor %sil, %al
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; idiv %al, %sil, %al
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cbtw
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; cmpb $0, %sil
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; jne 0x15
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; ud2 ; trap: int_divz
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; cmpb $0xff, %sil
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; jne 0x2a
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; cmpb $0x80, %al
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; jne 0x2a
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; ud2 ; trap: int_ovf
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; idivb %sil ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f2(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = sdiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; validate_sdiv_divisor %si, %di
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; movq %rdi, %rax
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; cwd %ax, %dx
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; idiv %ax, %dx, %si, %ax, %dx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; cmpw $0, %si
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; jne 0x10
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; ud2 ; trap: int_divz
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; cmpw $-1, %si
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; jne 0x27
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; cmpw $0x8000, %di
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; jne 0x27
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; ud2 ; trap: int_ovf
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; movq %rdi, %rax
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; cwtd
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; idivw %si ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f3(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sdiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; validate_sdiv_divisor %esi, %edi
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; movq %rdi, %rax
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; cdq %eax, %edx
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; idiv %eax, %edx, %esi, %eax, %edx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; cmpl $0, %esi
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; jne 0xf
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; ud2 ; trap: int_divz
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; cmpl $-1, %esi
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; jne 0x26
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; cmpl $0x80000000, %edi
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; jne 0x26
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; ud2 ; trap: int_ovf
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; movq %rdi, %rax
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; cltd
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; idivl %esi ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f4(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = sdiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; validate_sdiv_divisor %rsi, %rdi %rcx
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; movq %rdi, %rax
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; cqo %rax, %rdx
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; idiv %rax, %rdx, %rsi, %rax, %rdx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; cmpq $0, %rsi
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; jne 0x10
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; ud2 ; trap: int_divz
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; cmpq $-1, %rsi
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; jne 0x2f
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; movabsq $9223372036854775808, %rcx
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; cmpq %rcx, %rdi
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; jne 0x2f
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; ud2 ; trap: int_ovf
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; movq %rdi, %rax
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; cqto
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; idivq %rsi ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i8_imm(i8) -> i8 {
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block0(v0: i8):
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v1 = iconst.i8 17
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v2 = sdiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cbw %al, %al
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; movl $17, %edx
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; idiv %al, %dl, %al
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cbtw
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; movl $0x11, %edx
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; idivb %dl ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i16_imm(i16) -> i16 {
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block0(v0: i16):
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v1 = iconst.i16 17
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v2 = sdiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movl $17, %ecx
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; movq %rdi, %rax
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; cwd %ax, %dx
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; idiv %ax, %dx, %cx, %ax, %dx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movl $0x11, %ecx
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; movq %rdi, %rax
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; cwtd
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; idivw %cx ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i32_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 17
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v2 = sdiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movl $17, %ecx
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; movq %rdi, %rax
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; cdq %eax, %edx
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; idiv %eax, %edx, %ecx, %eax, %edx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movl $0x11, %ecx
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; movq %rdi, %rax
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; cltd
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; idivl %ecx ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i64_imm(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 17
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v2 = sdiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movl $17, %ecx
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; movq %rdi, %rax
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; cqo %rax, %rdx
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; idiv %rax, %rdx, %rcx, %rax, %rdx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movl $0x11, %ecx
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; movq %rdi, %rax
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; cqto
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; idivq %rcx ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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