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Remove non-existent x86 encoding for sshr_imm.i64x2

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This instruction does not exist in the SSE2 feature set; it can be added later with an VEX/EVEX encoding.
This commit is contained in:
Andrew Brown
2020-05-21 15:25:20 -07:00
parent df171f01b5
commit 5a32500518
2 changed files with 5 additions and 8 deletions
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3
cranelift/codegen/meta/src/isa/x86/encodings.rs
View File

@@ -2184,9 +2184,12 @@ fn define_simd(
let ushr_imm = ushr_imm.bind(vector(*ty, sse_vector_size)); let ushr_imm = ushr_imm.bind(vector(*ty, sse_vector_size));
e.enc_both_inferred(ushr_imm, rec_f_ib.opcodes(*opcodes).rrr(2)); e.enc_both_inferred(ushr_imm, rec_f_ib.opcodes(*opcodes).rrr(2));
// One exception: PSRAQ does not exist in for 64x2 in SSE2, it requires a higher CPU feature set.
if *ty != I64 {
let sshr_imm = sshr_imm.bind(vector(*ty, sse_vector_size)); let sshr_imm = sshr_imm.bind(vector(*ty, sse_vector_size));
e.enc_both_inferred(sshr_imm, rec_f_ib.opcodes(*opcodes).rrr(4)); e.enc_both_inferred(sshr_imm, rec_f_ib.opcodes(*opcodes).rrr(4));
} }
}
// SIMD integer comparisons // SIMD integer comparisons
{ {

6
cranelift/filetests/filetests/isa/x86/simd-bitwise-binemit.clif
View File

@@ -97,9 +97,3 @@ block0(v0: i32x4 [%xmm4]):
[-, %xmm4] v2 = sshr_imm v0, 10 ; bin: 66 0f 72 e4 0a [-, %xmm4] v2 = sshr_imm v0, 10 ; bin: 66 0f 72 e4 0a
return v2 return v2
} }
function %sshr_imm_i64x2(i64x2) -> i64x2 {
block0(v0: i64x2 [%xmm6]):
[-, %xmm6] v2 = sshr_imm v0, 42 ; bin: 66 0f 73 e6 2a
return v2
}