From 5a325005182db1433309187db270ef7849b2b2d5 Mon Sep 17 00:00:00 2001 From: Andrew Brown Date: Thu, 21 May 2020 15:25:20 -0700 Subject: [PATCH] Remove non-existent x86 encoding for sshr_imm.i64x2 This instruction does not exist in the SSE2 feature set; it can be added later with an VEX/EVEX encoding. --- cranelift/codegen/meta/src/isa/x86/encodings.rs | 7 +++++-- .../filetests/filetests/isa/x86/simd-bitwise-binemit.clif | 6 ------ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/cranelift/codegen/meta/src/isa/x86/encodings.rs b/cranelift/codegen/meta/src/isa/x86/encodings.rs index dad9d9bba5..dec0b87842 100644 --- a/cranelift/codegen/meta/src/isa/x86/encodings.rs +++ b/cranelift/codegen/meta/src/isa/x86/encodings.rs @@ -2184,8 +2184,11 @@ fn define_simd( let ushr_imm = ushr_imm.bind(vector(*ty, sse_vector_size)); e.enc_both_inferred(ushr_imm, rec_f_ib.opcodes(*opcodes).rrr(2)); - let sshr_imm = sshr_imm.bind(vector(*ty, sse_vector_size)); - e.enc_both_inferred(sshr_imm, rec_f_ib.opcodes(*opcodes).rrr(4)); + // One exception: PSRAQ does not exist in for 64x2 in SSE2, it requires a higher CPU feature set. + if *ty != I64 { + let sshr_imm = sshr_imm.bind(vector(*ty, sse_vector_size)); + e.enc_both_inferred(sshr_imm, rec_f_ib.opcodes(*opcodes).rrr(4)); + } } // SIMD integer comparisons diff --git a/cranelift/filetests/filetests/isa/x86/simd-bitwise-binemit.clif b/cranelift/filetests/filetests/isa/x86/simd-bitwise-binemit.clif index 599c58fd80..3d729de31f 100644 --- a/cranelift/filetests/filetests/isa/x86/simd-bitwise-binemit.clif +++ b/cranelift/filetests/filetests/isa/x86/simd-bitwise-binemit.clif @@ -97,9 +97,3 @@ block0(v0: i32x4 [%xmm4]): [-, %xmm4] v2 = sshr_imm v0, 10 ; bin: 66 0f 72 e4 0a return v2 } - -function %sshr_imm_i64x2(i64x2) -> i64x2 { -block0(v0: i64x2 [%xmm6]): -[-, %xmm6] v2 = sshr_imm v0, 42 ; bin: 66 0f 73 e6 2a - return v2 -}