T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add RISC-V encodings for spill and fill.

Browse Source 
Add a Stack() class for specifying operand constraints for values on the
stack.

Add encoding recipes for RISC-V spill and fill instructions. Don't
implement the encoding recipe functions yet since we don't have the
stack slot layout yet.
This commit is contained in:
Jakob Stoklund Olesen
2017-06-13 13:39:52 -07:00
parent ea8a8a95a8
commit 5336bbd4cc
6 changed files with 53 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
lib/cretonne/meta/isa/riscv/encodings.py
View File

@@ -6,8 +6,9 @@ from base import instructions as base
from base.immediates import intcc
from .defs import RV32, RV64
from .recipes import OPIMM, OPIMM32, OP, OP32, LUI, BRANCH, JALR, JAL
from .recipes import LOAD, STORE
from .recipes import R, Rshamt, Ricmp, I, Iicmp, Iret
from .recipes import U, UJ, UJcall, SB, SBzero
from .recipes import U, UJ, UJcall, SB, SBzero, GPsp, GPfi
from .settings import use_m
from cdsl.ast import Var
@@ -114,3 +115,11 @@ for inst, f3 in [
# is added by legalize_signature().
RV32.enc(base.x_return, Iret, JALR())
RV64.enc(base.x_return, Iret, JALR())
# Spill and fill.
RV32.enc(base.spill.i32, GPsp, STORE(0b010))
RV64.enc(base.spill.i32, GPsp, STORE(0b010))
RV64.enc(base.spill.i64, GPsp, STORE(0b011))
RV32.enc(base.fill.i32, GPfi, LOAD(0b010))
RV64.enc(base.fill.i32, GPfi, LOAD(0b010))
RV64.enc(base.fill.i64, GPfi, LOAD(0b011))