Use the target-lexicon crate.

This switches from a custom list of architectures to use the
target-lexicon crate.

 - "set is_64bit=1; isa x86" is replaced with "target x86_64", and
   similar for other architectures, and the `is_64bit` flag is removed
   entirely.

 - The `is_compressed` flag is removed too; it's no longer being used to
   control REX prefixes on x86-64, ARM and Thumb are separate
   architectures in target-lexicon, and we can figure out how to
   select RISC-V compressed encodings when we're ready.

cranelift/Cargo.toml

@@ -31,6 +31,7 @@ serde_derive = "1.0.8"
 term = "0.5.1"
 capstone = "0.3.1"
 wabt = { version = "0.3", optional = true }
+target-lexicon = "0.0.0"
 
 [features]
 default = ["wasm"]

cranelift/docs/testing.rst

@@ -125,15 +125,15 @@ The ``set`` lines apply settings cumulatively::
 
     test legalizer
     set opt_level=best
-    set is_64bit=1
-    isa riscv
-    set is_64bit=0
-    isa riscv supports_m=false
+    set is_pic=1
+    isa riscv64
+    set is_pic=0
+    isa riscv32 supports_m=false
 
     function %foo() {}
 
 This example will run the legalizer test twice. Both runs will have
-``opt_level=best``, but they will have different ``is_64bit`` settings. The 32-bit
+``opt_level=best``, but they will have different ``is_pic`` settings. The 32-bit
 run will also have the RISC-V specific flag ``supports_m`` disabled.
 
 The filetests are run automatically as part of `cargo test`, and they can

cranelift/filetests/isa/riscv/abi-e.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of function signatures for RV32E.
 test legalizer
-isa riscv enable_e
+target riscv32 enable_e
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/abi.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of function signatures.
 test legalizer
-isa riscv
+target riscv32
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/binary32.cton

@@ -1,6 +1,6 @@
 ; Binary emission of 32-bit code.
 test binemit
-isa riscv
+target riscv32
 
 function %RV32I(i32 link [%x1]) -> i32 link [%x1] {
     sig0 = ()

cranelift/filetests/isa/riscv/encoding.cton

@@ -1,5 +1,5 @@
 test legalizer
-isa riscv supports_m=1
+target riscv32 supports_m=1
 
 function %int32(i32, i32) {
 ebb0(v1: i32, v2: i32):

cranelift/filetests/isa/riscv/expand-i32.cton

@@ -1,11 +1,9 @@
 ; Test the legalization of i32 instructions that don't have RISC-V versions.
 test legalizer
 
-set is_64bit=0
-isa riscv supports_m=1
+target riscv32 supports_m=1
 
-set is_64bit=1
-isa riscv supports_m=1
+target riscv64 supports_m=1
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/legalize-abi.cton

@@ -1,6 +1,6 @@
 ; Test legalizer's handling of ABI boundaries.
 test legalizer
-isa riscv
+target riscv32
 
 ; regex: V=v\d+
 ; regex: SS=ss\d+

cranelift/filetests/isa/riscv/legalize-i64.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of i64 arithmetic instructions.
 test legalizer
-isa riscv supports_m=1
+target riscv32 supports_m=1
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/parse-encoding.cton

@@ -1,6 +1,6 @@
 ; Test the parser's support for encoding annotations.
 test legalizer
-isa riscv
+target riscv32
 
 function %parse_encoding(i32 [%x5]) -> i32 [%x10] {
     ; check: function %parse_encoding(i32 [%x5], i32 link [%x1]) -> i32 [%x10], i32 link [%x1] fast {

cranelift/filetests/isa/riscv/regmove.cton

@@ -1,6 +1,6 @@
 ; Test tracking of register moves.
 test binemit
-isa riscv
+target riscv32
 
 function %regmoves(i32 link [%x1]) -> i32 link [%x1] {
 ebb0(v9999: i32):

cranelift/filetests/isa/riscv/split-args.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of EBB arguments that are split.
 test legalizer
-isa riscv
+target riscv32
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/riscv/verify-encoding.cton

@@ -1,5 +1,5 @@
 test verifier
-isa riscv
+target riscv32
 
 function %RV32I(i32 link [%x1]) -> i32 link [%x1] {
     fn0 = %foo()

cranelift/filetests/isa/x86/abcd.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa x86
+target i686
 
 ; %rdi can't be used in a movsbl instruction, so test that the register
 ; allocator can move it to a register that can be.

cranelift/filetests/isa/x86/abi-bool.cton

@@ -1,6 +1,5 @@
 test compile
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %foo(i64, i64, i64, i32) -> b1 system_v {
 ebb3(v0: i64, v1: i64, v2: i64, v3: i32):

cranelift/filetests/isa/x86/abi32.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of function signatures.
 test legalizer
-isa x86
+target i686
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/x86/abi64.cton

@@ -1,7 +1,6 @@
 ; Test the legalization of function signatures.
 test legalizer
-set is_64bit
-isa x86
+target x86_64
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/x86/allones_funcaddrs32.cton

@@ -2,7 +2,7 @@
 test binemit
 set opt_level=best
 set allones_funcaddrs
-isa x86 haswell
+target i686 haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/isa/x86/allones_funcaddrs64.cton

@@ -1,9 +1,8 @@
 ; binary emission of 64-bit code.
 test binemit
-set is_64bit
 set opt_level=best
 set allones_funcaddrs
-isa x86 haswell
+target x86_64 haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/isa/x86/baseline_clz_ctz_popcount.cton

@@ -1,7 +1,5 @@
-
 test compile
-set is_64bit
-isa x86 baseline
+target x86_64 baseline
 
 
 ; clz/ctz on 64 bit operands

cranelift/filetests/isa/x86/baseline_clz_ctz_popcount_encoding.cton

@@ -1,7 +1,6 @@
 test binemit
-set is_64bit
 set opt_level=best
-isa x86 baseline
+target x86_64 baseline
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/isa/x86/binary32-float.cton

@@ -1,6 +1,6 @@
 ; Binary emission of 32-bit floating point code.
 test binemit
-isa x86 haswell
+target i686 haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/isa/x86/binary32.cton

@@ -1,7 +1,7 @@
 ; binary emission of x86-32 code.
 test binemit
 set opt_level=best
-isa x86 haswell
+target i686 haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/isa/x86/binary64-float.cton

@@ -1,8 +1,7 @@
 ; Binary emission of 64-bit floating point code.
 test binemit
-set is_64bit
 set opt_level=best
-isa x86 haswell
+target x86_64 haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/isa/x86/binary64-pic.cton

@@ -1,9 +1,8 @@
 ; binary emission of 64-bit code.
 test binemit
-set is_64bit
 set opt_level=best
 set is_pic
-isa x86 haswell
+target x86_64 haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/isa/x86/binary64.cton

@@ -1,8 +1,7 @@
 ; binary emission of x86-64 code.
 test binemit
-set is_64bit
 set opt_level=best
-isa x86 haswell
+target x86_64 haswell
 
 ; The binary encodings can be verified with the command:
 ;

cranelift/filetests/isa/x86/legalize-call.cton

@@ -1,8 +1,7 @@
 ; Test legalization of a non-colocated call in 64-bit non-PIC mode.
 test legalizer
-set is_64bit
 set opt_level=best
-isa x86 haswell
+target x86_64 haswell
 
 function %call() {
     fn0 = %foo()

cranelift/filetests/isa/x86/legalize-custom.cton

@@ -1,8 +1,7 @@
 ; Test the custom legalizations.
 test legalizer
-isa x86
-set is_64bit
-isa x86
+target i686
+target x86_64
 
 ; regex: V=v\d+
 ; regex: EBB=ebb\d+

cranelift/filetests/isa/x86/legalize-div-traps.cton

@@ -1,9 +1,8 @@
 ; Test the division legalizations.
 test legalizer
-set is_64bit
 ; See also legalize-div.cton.
 set avoid_div_traps=1
-isa x86
+target x86_64
 
 ; regex: V=v\d+
 ; regex: EBB=ebb\d+

cranelift/filetests/isa/x86/legalize-div.cton

@@ -1,9 +1,8 @@
 ; Test the division legalizations.
 test legalizer
-set is_64bit
 ; See also legalize-div-traps.cton.
 set avoid_div_traps=0
-isa x86
+target x86_64
 
 ; regex: V=v\d+
 ; regex: EBB=ebb\d+

cranelift/filetests/isa/x86/legalize-libcall.cton

@@ -1,10 +1,9 @@
 test legalizer
 
 ; Pre-SSE 4.1, we need to use runtime library calls for floating point rounding operations.
-set is_64bit
 set is_pic
 set call_conv=system_v
-isa x86
+target x86_64
 
 function %floor(f32) -> f32 {
 ebb0(v0: f32):

cranelift/filetests/isa/x86/legalize-memory.cton

@@ -1,7 +1,6 @@
 ; Test the legalization of memory objects.
 test legalizer
-set is_64bit
-isa x86
+target x86_64
 
 ; regex: V=v\d+
 ; regex: EBB=ebb\d+

cranelift/filetests/isa/x86/legalize-mulhi.cton

@@ -1,7 +1,5 @@
-
 test compile
-set is_64bit
-isa x86 baseline
+target x86_64 baseline
 
 ; umulhi/smulhi on 64 bit operands
 

cranelift/filetests/isa/x86/optimized-zero-constants-32bit.cton

@@ -1,7 +1,6 @@
 ; Check that floating-point constants equal to zero are optimized correctly.
 test binemit
-set is_64bit=0
-isa x86
+target i686
 
 function %foo() -> f32 fast {
 ebb0:

cranelift/filetests/isa/x86/optimized-zero-constants.cton

@@ -1,7 +1,6 @@
 ; Check that floating-point constants equal to zero are optimized correctly.
 test binemit
-set is_64bit=1
-isa x86
+target x86_64
 
 function %zero_const_32bit_no_rex() -> f32 fast {
 ebb0:

cranelift/filetests/isa/x86/probestack-adjusts-sp.cton

@@ -1,8 +1,7 @@
 test compile
-set is_64bit=1
 set colocated_libcalls=1
 set probestack_func_adjusts_sp=1
-isa x86
+target x86_64
 
 ; Like %big in probestack.cton, but with the probestack function adjusting
 ; the stack pointer itself.

cranelift/filetests/isa/x86/probestack-disabled.cton

@@ -1,8 +1,7 @@
 test compile
-set is_64bit=1
 set colocated_libcalls=1
 set probestack_enabled=0
-isa x86
+target x86_64
 
 ; Like %big in probestack.cton, but with probes disabled.
 

cranelift/filetests/isa/x86/probestack-noncolocated.cton

@@ -1,6 +1,5 @@
 test compile
-set is_64bit=1
-isa x86
+target x86_64
 
 ; Like %big in probestack.cton, but without a colocated libcall.
 

cranelift/filetests/isa/x86/probestack-size.cton

@@ -1,8 +1,7 @@
 test compile
-set is_64bit=1
 set colocated_libcalls=1
 set probestack_size_log2=13
-isa x86
+target x86_64
 
 ; Like %big in probestack.cton, but now the probestack size is bigger
 ; and it no longer needs a probe.

cranelift/filetests/isa/x86/probestack.cton

@@ -1,7 +1,6 @@
 test compile
-set is_64bit=1
 set colocated_libcalls=1
-isa x86
+target x86_64
 
 ; A function with a big stack frame. This should have a stack probe.
 

cranelift/filetests/isa/x86/prologue-epilogue.cton

@@ -1,8 +1,7 @@
 test compile
-set is_64bit
 set opt_level=best
 set is_pic
-isa x86 haswell
+target x86_64 haswell
 
 ; An empty function.
 

cranelift/filetests/isa/x86/shrink.cton

@@ -1,7 +1,6 @@
 test binemit
-set is_64bit=1
 set opt_level=best
-isa x86
+target x86_64
 
 ; Test that instruction shrinking eliminates REX prefixes when possible.
 

cranelift/filetests/isa/x86/windows_fastcall_x64.cton

@@ -1,8 +1,7 @@
 test compile
-set is_64bit
 set opt_level=best
 set is_pic
-isa x86 haswell
+target x86_64 haswell
 
 ; check if for one arg we use the right register
 function %one_arg(i64) windows_fastcall {

cranelift/filetests/parser/instruction_encoding.cton

@@ -1,6 +1,6 @@
 test cat
 
-isa riscv
+target riscv32
 
 ; regex: WS=[ \t]*
 

cranelift/filetests/postopt/basic.cton

@@ -1,5 +1,5 @@
 test postopt
-isa x86
+target i686
 
 ; Test that compare+branch sequences are folded effectively on x86.
 

cranelift/filetests/postopt/complex_memory_ops.cton

@@ -1,6 +1,5 @@
 test postopt
-set is_64bit
-isa x86
+target x86_64
 
 function %dual_loads(i64, i64) -> i64 {
 ebb0(v0: i64, v1: i64):

cranelift/filetests/preopt/div_by_const_indirect.cton

@@ -1,6 +1,5 @@
-
 test preopt
-isa x86 baseline
+target i686 baseline
 
 ; Cases where the denominator is created by an iconst
 

cranelift/filetests/preopt/div_by_const_non_power_of_2.cton

@@ -1,6 +1,5 @@
-
 test preopt
-isa x86 baseline
+target i686 baseline
 
 ; -------- U32 --------
 

cranelift/filetests/preopt/div_by_const_power_of_2.cton

@@ -1,6 +1,5 @@
-
 test preopt
-isa x86 baseline
+target i686 baseline
 
 ; -------- U32 --------
 

cranelift/filetests/preopt/rem_by_const_non_power_of_2.cton

@@ -1,6 +1,5 @@
-
 test preopt
-isa x86 baseline
+target i686 baseline
 
 ; -------- U32 --------
 

cranelift/filetests/preopt/rem_by_const_power_of_2.cton

@@ -1,6 +1,5 @@
-
 test preopt
-isa x86 baseline
+target i686 baseline
 
 ; -------- U32 --------
 

cranelift/filetests/preopt/simplify.cton

@@ -1,5 +1,5 @@
 test preopt
-isa x86
+target i686
 
 function %iadd_imm(i32) -> i32 {
 ebb0(v0: i32):

cranelift/filetests/regalloc/aliases.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell
 
 function %value_aliases(i32, f32, i64 vmctx) baldrdash {
     gv0 = vmctx

cranelift/filetests/regalloc/basic.cton

@@ -1,7 +1,7 @@
 test regalloc
 
 ; We can add more ISAs once they have defined encodings.
-isa riscv
+target riscv32
 
 ; regex: RX=%x\d+
 

cranelift/filetests/regalloc/coalesce.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa riscv
+target riscv32
 
 ; Test the coalescer.
 ; regex: V=v\d+

cranelift/filetests/regalloc/coalescing-207.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell
 
 ; Reported as https://github.com/cretonne/cretonne/issues/207
 ;

cranelift/filetests/regalloc/coalescing-216.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell
 
 ; Reported as https://github.com/cretonne/cretonne/issues/216 from the Binaryen fuzzer.
 ;

cranelift/filetests/regalloc/coloring-227.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell
 
 function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8]) system_v {
     gv0 = vmctx

cranelift/filetests/regalloc/constraints.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa x86
+target i686
 
 ; regex: V=v\d+
 ; regex: REG=%r([abcd]x|[sd]i)

cranelift/filetests/regalloc/ghost-param.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell
 
 ; This test case would create an EBB parameter that was a ghost value.
 ; The coalescer would insert a copy of the ghost value, leading to verifier errors.

cranelift/filetests/regalloc/global-constraints.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa x86
+target i686
 
 ; This test covers the troubles when values with global live ranges are defined
 ; by instructions with constrained register classes.

cranelift/filetests/regalloc/global-fixed.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %foo() system_v {
 ebb4:

cranelift/filetests/regalloc/infinite-interference.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa riscv
+target riscv32
 
 ; Here, the coalescer initially builds vreg0 = [v1, v2, v3]
 ;

cranelift/filetests/regalloc/iterate.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell
 
 function u0:9(i64 [%rdi], f32 [%xmm0], f64 [%xmm1], i32 [%rsi], i32 [%rdx], i64 vmctx [%r14]) -> i64 [%rax] baldrdash {
 ebb0(v0: i64, v1: f32, v2: f64, v3: i32, v4: i32, v5: i64):

cranelift/filetests/regalloc/multi-constraints.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell
 
 ; Test combinations of constraints.
 ;

cranelift/filetests/regalloc/output-interference.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %test(i64) -> i64 system_v {
 ebb0(v0: i64):

cranelift/filetests/regalloc/reload-208.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86 haswell
+target x86_64 haswell
 
 ; regex: V=v\d+
 

cranelift/filetests/regalloc/reload.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa riscv enable_e
+target riscv32 enable_e
 
 ; regex: V=v\d+
 

cranelift/filetests/regalloc/schedule-moves.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa x86 haswell
+target i686 haswell
 
 function %pr165() system_v {
 ebb0:

cranelift/filetests/regalloc/spill-noregs.cton

@@ -1,6 +1,5 @@
 test regalloc
-set is_64bit
-isa x86
+target x86_64
 
 ; Test case found by the Binaryen fuzzer.
 ;

cranelift/filetests/regalloc/spill.cton

@@ -12,7 +12,7 @@ test regalloc
 ; regex: V=v\d+
 ; regex: WS=\s+
 
-isa riscv enable_e
+target riscv32 enable_e
 
 ; In straight-line code, the first value defined is spilled.
 ; That is in order:

cranelift/filetests/regalloc/unreachable_code.cton

@@ -1,9 +1,8 @@
 ; Use "test compile" here otherwise the dead blocks won't be eliminated.
 test compile
 
-set is_64bit
 set probestack_enabled=0
-isa x86 haswell
+target x86_64 haswell
 
 ; This function contains unreachable blocks which trip up the register
 ; allocator if they don't get cleared out.

cranelift/filetests/regalloc/x86-regres.cton

@@ -1,6 +1,6 @@
 test regalloc
 
-isa x86
+target i686
 
 ; regex: V=v\d+
 

cranelift/filetests/verifier/flags.cton

@@ -1,5 +1,5 @@
 test verifier
-isa x86
+target i686
 
 ; Simple, correct use of CPU flags.
 function %simple(i32) -> i32 {

cranelift/filetests/wasm/control.cton

@@ -1,11 +1,9 @@
 ; Test basic code generation for control flow WebAssembly instructions.
 test compile
 
-set is_64bit=0
-isa x86 haswell
+target i686 haswell
 
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %br_if(i32) -> i32 {
 ebb0(v0: i32):

cranelift/filetests/wasm/conversions.cton

@@ -1,8 +1,7 @@
 ; Test code generation for WebAssembly type conversion operators.
 test compile
 
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %i32_wrap_i64(i64) -> i32 {
 ebb0(v0: i64):

cranelift/filetests/wasm/f32-arith.cton

@@ -1,17 +1,10 @@
 ; Test basic code generation for f32 arithmetic WebAssembly instructions.
 test compile
 
-set is_64bit=0
-isa x86 haswell
-
-set is_64bit=0
-isa x86 baseline
-
-set is_64bit=1
-isa x86 haswell
-
-set is_64bit=1
-isa x86 baseline
+target i686 haswell
+target i686 baseline
+target x86_64 haswell
+target x86_64 baseline
 
 ; Constants.
 

cranelift/filetests/wasm/f32-compares.cton

@@ -1,11 +1,9 @@
 ; Test code generation for WebAssembly f32 comparison operators.
 test compile
 
-set is_64bit=0
-isa x86 haswell
+target i686 haswell
 
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %f32_eq(f32, f32) -> i32 {
 ebb0(v0: f32, v1: f32):

cranelift/filetests/wasm/f32-memory64.cton

@@ -3,8 +3,7 @@ test compile
 
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %f32_load(i32, i64 vmctx) -> f32 {
     gv0 = vmctx

cranelift/filetests/wasm/f64-arith.cton

@@ -1,11 +1,8 @@
 ; Test basic code generation for f64 arithmetic WebAssembly instructions.
 test compile
 
-set is_64bit=1
-isa x86 haswell
-
-set is_64bit=1
-isa x86 baseline
+target x86_64 haswell
+target x86_64 baseline
 
 ; Constants.
 

cranelift/filetests/wasm/f64-compares.cton

@@ -1,11 +1,9 @@
 ; Test code generation for WebAssembly f64 comparison operators.
 test compile
 
-set is_64bit=0
-isa x86 haswell
+target i686 haswell
 
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %f64_eq(f64, f64) -> i32 {
 ebb0(v0: f64, v1: f64):

cranelift/filetests/wasm/f64-memory64.cton

@@ -3,8 +3,7 @@ test compile
 
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %f64_load(i32, i64 vmctx) -> f64 {
     gv0 = vmctx

cranelift/filetests/wasm/i32-arith.cton

@@ -1,17 +1,10 @@
 ; Test basic code generation for i32 arithmetic WebAssembly instructions.
 test compile
 
-set is_64bit=0
-isa x86 haswell
-
-set is_64bit=0
-isa x86 baseline
-
-set is_64bit=1
-isa x86 haswell
-
-set is_64bit=1
-isa x86 baseline
+target i686 haswell
+target i686 baseline
+target x86_64 haswell
+target x86_64 baseline
 
 ; Constants.
 

cranelift/filetests/wasm/i32-compares.cton

@@ -1,11 +1,9 @@
 ; Test code generation for WebAssembly i32 comparison operators.
 test compile
 
-set is_64bit=0
-isa x86 haswell
+target i686 haswell
 
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %i32_eqz(i32) -> i32 {
 ebb0(v0: i32):

cranelift/filetests/wasm/i32-memory64.cton

@@ -3,8 +3,7 @@ test compile
 
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %i32_load(i32, i64 vmctx) -> i32 {
     gv0 = vmctx

cranelift/filetests/wasm/i64-arith.cton

@@ -1,11 +1,8 @@
 ; Test basic code generation for i64 arithmetic WebAssembly instructions.
 test compile
 
-set is_64bit=1
-isa x86 haswell
-
-set is_64bit=1
-isa x86 baseline
+target x86_64 haswell
+target x86_64 baseline
 
 ; Constants.
 

cranelift/filetests/wasm/i64-compares.cton

@@ -1,8 +1,7 @@
 ; Test code generation for WebAssembly i64 comparison operators.
 test compile
 
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %i64_eqz(i64) -> i32 {
 ebb0(v0: i64):

cranelift/filetests/wasm/i64-memory64.cton

@@ -3,8 +3,7 @@ test compile
 
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %i64_load(i32, i64 vmctx) -> i64 {
     gv0 = vmctx

cranelift/filetests/wasm/select.cton

@@ -1,11 +1,9 @@
 ; Test basic code generation for the select WebAssembly instruction.
 test compile
 
-set is_64bit=0
-isa x86 haswell
+target i686 haswell
 
-set is_64bit=1
-isa x86 haswell
+target x86_64 haswell
 
 function %select_i32(i32, i32, i32) -> i32 {
 ebb0(v0: i32, v1: i32, v2: i32):

cranelift/fuzz/Cargo.toml

@@ -20,6 +20,9 @@ git = "https://github.com/rust-fuzz/libfuzzer-sys.git"
 [dependencies.cretonne-wasm]
 path = "../lib/wasm"
 
+[dependencies.target-lexicon]
+version = "0.0.0"
+
 # Prevent this from interfering with workspaces
 [workspace]
 members = ["."]

cranelift/fuzz/fuzz_translate_module.rs

@@ -3,13 +3,16 @@
 extern crate libfuzzer_sys;
 extern crate binaryen;
 extern crate cretonne_wasm;
+#[macro_use]
+extern crate target_lexicon;
 use cretonne_wasm::{translate_module, DummyEnvironment};
+use std::str::FromStr;
 
 fuzz_target!(|data: &[u8]| {
     let binaryen_module = binaryen::tools::translate_to_fuzz_mvp(data);
 
     let wasm = binaryen_module.write();
 
-    let mut dummy_environ = DummyEnvironment::default();
+    let mut dummy_environ = DummyEnvironment::with_triple(triple!("x86_64"));
     translate_module(&wasm, &mut dummy_environ).unwrap();
 });

cranelift/src/compile.rs

@@ -9,7 +9,8 @@ use cretonne_codegen::{binemit, ir};
 use cretonne_reader::parse_test;
 use std::path::Path;
 use std::path::PathBuf;
-use utils::{parse_sets_and_isa, read_to_string};
+use target_lexicon::Architecture;
+use utils::{parse_sets_and_triple, read_to_string};
 
 struct PrintRelocs {
     flag_print: bool,
@@ -64,7 +65,7 @@ pub fn run(
     flag_set: &[String],
     flag_isa: &str,
 ) -> Result<(), String> {
-    let parsed = parse_sets_and_isa(flag_set, flag_isa)?;
+    let parsed = parse_sets_and_triple(flag_set, flag_isa)?;
 
     for filename in files {
         let path = Path::new(&filename);
@@ -136,23 +137,28 @@ fn handle_module(
 }
 
 fn get_disassembler(isa: &TargetIsa) -> Result<Capstone, String> {
-    let cs = match isa.name() {
-        "riscv" => return Err(String::from("No disassembler for RiscV")),
-        "x86" => {
-            if isa.flags().is_64bit() {
-                Capstone::new()
-                    .x86()
-                    .mode(arch::x86::ArchMode::Mode64)
-                    .build()
-            } else {
-                Capstone::new()
+    let cs = match isa.triple().architecture {
+        Architecture::Riscv32 | Architecture::Riscv64 => {
+            return Err(String::from("No disassembler for RiscV"))
+        }
+        Architecture::I386 | Architecture::I586 | Architecture::I686 => Capstone::new()
             .x86()
             .mode(arch::x86::ArchMode::Mode32)
-                    .build()
-            }
-        }
-        "arm32" => Capstone::new().arm().mode(arch::arm::ArchMode::Arm).build(),
-        "arm64" => Capstone::new()
+            .build(),
+        Architecture::X86_64 => Capstone::new()
+            .x86()
+            .mode(arch::x86::ArchMode::Mode64)
+            .build(),
+        Architecture::Arm
+        | Architecture::Armv4t
+        | Architecture::Armv5te
+        | Architecture::Armv7
+        | Architecture::Armv7s => Capstone::new().arm().mode(arch::arm::ArchMode::Arm).build(),
+        Architecture::Thumbv6m | Architecture::Thumbv7em | Architecture::Thumbv7m => Capstone::new(
+        ).arm()
+            .mode(arch::arm::ArchMode::Thumb)
+            .build(),
+        Architecture::Aarch64 => Capstone::new()
             .arm64()
             .mode(arch::arm64::ArchMode::Arm)
             .build(),

cranelift/src/cton-util.rs

@@ -27,6 +27,7 @@ cfg_if! {
         mod wasm;
     }
 }
+extern crate target_lexicon;
 
 use cretonne_codegen::{timing, VERSION};
 use docopt::Docopt;
@@ -47,8 +48,8 @@ Usage:
     cton-util cat <file>...
     cton-util filecheck [-v] <file>
     cton-util print-cfg <file>...
-    cton-util compile [-vpT] [--set <set>]... [--isa <isa>] <file>...
-    cton-util wasm [-ctvpTs] [--set <set>]... [--isa <isa>] <file>...
+    cton-util compile [-vpT] [--set <set>]... [--target <triple>] <file>...
+    cton-util wasm [-ctvpTs] [--set <set>]... [--target <triple>] <file>...
     cton-util --help | --version
 
 Options:
@@ -64,7 +65,8 @@ Options:
     -p, --print     print the resulting Cretonne IR
     -h, --help      print this help message
     --set=<set>     configure Cretonne settings
-    --isa=<isa>     specify the Cretonne ISA
+    --target=<triple>
+                    specify the Cretonne target
     --version       print the Cretonne version
 
 ";
@@ -83,7 +85,7 @@ struct Args {
     flag_print: bool,
     flag_verbose: bool,
     flag_set: Vec<String>,
-    flag_isa: String,
+    flag_target: String,
     flag_time_passes: bool,
     flag_print_size: bool,
 }
@@ -116,7 +118,7 @@ fn cton_util() -> CommandResult {
             args.arg_file,
             args.flag_print,
             &args.flag_set,
-            &args.flag_isa,
+            &args.flag_target,
         )
     } else if args.cmd_wasm {
         #[cfg(feature = "wasm")]
@@ -127,7 +129,7 @@ fn cton_util() -> CommandResult {
             args.flag_check_translation,
             args.flag_print,
             &args.flag_set,
-            &args.flag_isa,
+            &args.flag_target,
             args.flag_print_size,
         );
 

cranelift/src/utils.rs

@@ -7,6 +7,8 @@ use cretonne_reader::{parse_options, Location};
 use std::fs::File;
 use std::io::{self, Read};
 use std::path::Path;
+use std::str::FromStr;
+use target_lexicon::Triple;
 
 /// Read an entire file into a string.
 pub fn read_to_string<P: AsRef<Path>>(path: P) -> io::Result<String> {
@@ -40,8 +42,11 @@ impl OwnedFlagsOrIsa {
     }
 }
 
-/// Parse "set" and "isa" commands.
-pub fn parse_sets_and_isa(flag_set: &[String], flag_isa: &str) -> Result<OwnedFlagsOrIsa, String> {
+/// Parse "set" and "triple" commands.
+pub fn parse_sets_and_triple(
+    flag_set: &[String],
+    flag_triple: &str,
+) -> Result<OwnedFlagsOrIsa, String> {
     let mut flag_builder = settings::builder();
     parse_options(
         flag_set.iter().map(|x| x.as_str()),
@@ -49,12 +54,21 @@ pub fn parse_sets_and_isa(flag_set: &[String], flag_isa: &str) -> Result<OwnedFl
         &Location { line_number: 0 },
     ).map_err(|err| err.to_string())?;
 
-    let mut words = flag_isa.trim().split_whitespace();
-    // Look for `isa foo`.
-    if let Some(isa_name) = words.next() {
-        let mut isa_builder = isa::lookup(isa_name).map_err(|err| match err {
-            isa::LookupError::Unknown => format!("unknown ISA '{}'", isa_name),
-            isa::LookupError::Unsupported => format!("support for ISA '{}' not enabled", isa_name),
+    let mut words = flag_triple.trim().split_whitespace();
+    // Look for `target foo`.
+    if let Some(triple_name) = words.next() {
+        let triple = match Triple::from_str(triple_name) {
+            Ok(triple) => triple,
+            Err(parse_error) => return Err(format!("{}", parse_error)),
+        };
+        let mut isa_builder = isa::lookup(triple).map_err(|err| match err {
+            isa::LookupError::SupportDisabled => {
+                format!("support for triple '{}' is disabled", triple_name)
+            }
+            isa::LookupError::Unsupported => format!(
+                "support for triple '{}' is not implemented yet",
+                triple_name
+            ),
         })?;
         // Apply the ISA-specific settings to `isa_builder`.
         parse_options(words, &mut isa_builder, &Location { line_number: 0 })

cranelift/src/wasm.rs

@@ -12,7 +12,7 @@ use std::error::Error;
 use std::path::Path;
 use std::path::PathBuf;
 use term;
-use utils::{parse_sets_and_isa, read_to_end};
+use utils::{parse_sets_and_triple, read_to_end};
 use wabt::wat2wasm;
 
 macro_rules! vprintln {
@@ -38,10 +38,10 @@ pub fn run(
     flag_check_translation: bool,
     flag_print: bool,
     flag_set: &[String],
-    flag_isa: &str,
+    flag_triple: &str,
     flag_print_size: bool,
 ) -> Result<(), String> {
-    let parsed = parse_sets_and_isa(flag_set, flag_isa)?;
+    let parsed = parse_sets_and_triple(flag_set, flag_triple)?;
 
     for filename in files {
         let path = Path::new(&filename);
@@ -79,9 +79,7 @@ fn handle_module(
     vprint!(flag_verbose, "Translating... ");
     terminal.reset().unwrap();
 
-    let mut data = read_to_end(path.clone()).map_err(|err| {
-        String::from(err.description())
-    })?;
+    let mut data = read_to_end(path.clone()).map_err(|err| String::from(err.description()))?;
 
     if !data.starts_with(&[b'\0', b'a', b's', b'm']) {
         data = match wat2wasm(&data) {
@@ -90,10 +88,9 @@ fn handle_module(
         };
     }
 
-    let mut dummy_environ = DummyEnvironment::with_flags(fisa.flags.clone());
-    translate_module(&data, &mut dummy_environ).map_err(
-        |e| e.to_string(),
-    )?;
+    let mut dummy_environ =
+        DummyEnvironment::with_triple_flags(fisa.isa.unwrap().triple().clone(), fisa.flags.clone());
+    translate_module(&data, &mut dummy_environ).map_err(|e| e.to_string())?;
 
     terminal.fg(term::color::GREEN).unwrap();
     vprintln!(flag_verbose, "ok");
@@ -142,24 +139,22 @@ fn handle_module(
         let mut context = Context::new();
         context.func = func.clone();
         if flag_check_translation {
-            context.verify(fisa).map_err(|err| {
-                pretty_verifier_error(&context.func, fisa.isa, &err)
-            })?;
+            context
+                .verify(fisa)
+                .map_err(|err| pretty_verifier_error(&context.func, fisa.isa, &err))?;
         } else if let Some(isa) = fisa.isa {
-            let compiled_size = context.compile(isa).map_err(|err| {
-                pretty_error(&context.func, fisa.isa, err)
-            })?;
+            let compiled_size = context
+                .compile(isa)
+                .map_err(|err| pretty_error(&context.func, fisa.isa, err))?;
             if flag_print_size {
                 println!(
                     "Function #{} code size: {} bytes",
-                    func_index,
-                    compiled_size
+                    func_index, compiled_size
                 );
                 total_module_code_size += compiled_size;
                 println!(
                     "Function #{} bytecode size: {} bytes",
-                    func_index,
-                    dummy_environ.func_bytecode_sizes[def_index]
+                    func_index, dummy_environ.func_bytecode_sizes[def_index]
                 );
             }
         } else {

lib/codegen/Cargo.toml

@@ -15,6 +15,7 @@ cretonne-entity = { path = "../entity", version = "0.8.0", default-features = fa
 failure = { version = "0.1.1", default-features = false, features = ["derive"] }
 failure_derive = { version = "0.1.1", default-features = false }
 hashmap_core = { version = "0.1.4", optional = true }
+target-lexicon = { version = "0.0.0", default-features = false }
 # It is a goal of the cretonne-codegen crate to have minimal external dependencies.
 # Please don't add any unless they are essential to the task of creating binary
 # machine code. Integration tests that need external dependencies can be

lib/codegen/meta/base/settings.py

@@ -27,8 +27,6 @@ enable_verifier = BoolSetting(
         """,
         default=True)
 
-is_64bit = BoolSetting("Enable 64-bit code generation")
-
 call_conv = EnumSetting(
         """
         Default calling convention:
@@ -89,8 +87,6 @@ avoid_div_traps = BoolSetting(
         this setting has no effect - explicit checks are always inserted.
         """)
 
-is_compressed = BoolSetting("Enable compressed instructions")
-
 enable_float = BoolSetting(
         """
         Enable the use of floating-point instructions

lib/codegen/src/isa/arm32/mod.rs

@@ -15,32 +15,43 @@ use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use regalloc;
 use std::boxed::Box;
 use std::fmt;
+use target_lexicon::{Architecture, Triple};
 
 #[allow(dead_code)]
 struct Isa {
+    triple: Triple,
     shared_flags: shared_settings::Flags,
     isa_flags: settings::Flags,
     cpumode: &'static [shared_enc_tables::Level1Entry<u16>],
 }
 
 /// Get an ISA builder for creating ARM32 targets.
-pub fn isa_builder() -> IsaBuilder {
+pub fn isa_builder(triple: Triple) -> IsaBuilder {
     IsaBuilder {
+        triple,
         setup: settings::builder(),
         constructor: isa_constructor,
     }
 }
 
 fn isa_constructor(
+    triple: Triple,
     shared_flags: shared_settings::Flags,
     builder: shared_settings::Builder,
 ) -> Box<TargetIsa> {
-    let level1 = if shared_flags.is_compressed() {
+    let level1 = match triple.architecture {
+        Architecture::Thumbv6m | Architecture::Thumbv7em | Architecture::Thumbv7m => {
             &enc_tables::LEVEL1_T32[..]
-    } else {
-        &enc_tables::LEVEL1_A32[..]
+        }
+        Architecture::Arm
+        | Architecture::Armv4t
+        | Architecture::Armv5te
+        | Architecture::Armv7
+        | Architecture::Armv7s => &enc_tables::LEVEL1_A32[..],
+        _ => panic!(),
     };
     Box::new(Isa {
+        triple,
         isa_flags: settings::Flags::new(&shared_flags, builder),
         shared_flags,
         cpumode: level1,
@@ -52,6 +63,10 @@ impl TargetIsa for Isa {
         "arm32"
     }
 
+    fn triple(&self) -> &Triple {
+        &self.triple
+    }
+
     fn flags(&self) -> &shared_settings::Flags {
         &self.shared_flags
     }

lib/codegen/src/isa/arm64/mod.rs

@@ -15,26 +15,31 @@ use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use regalloc;
 use std::boxed::Box;
 use std::fmt;
+use target_lexicon::Triple;
 
 #[allow(dead_code)]
 struct Isa {
+    triple: Triple,
     shared_flags: shared_settings::Flags,
     isa_flags: settings::Flags,
 }
 
 /// Get an ISA builder for creating ARM64 targets.
-pub fn isa_builder() -> IsaBuilder {
+pub fn isa_builder(triple: Triple) -> IsaBuilder {
     IsaBuilder {
+        triple,
         setup: settings::builder(),
         constructor: isa_constructor,
     }
 }
 
 fn isa_constructor(
+    triple: Triple,
     shared_flags: shared_settings::Flags,
     builder: shared_settings::Builder,
 ) -> Box<TargetIsa> {
     Box::new(Isa {
+        triple,
         isa_flags: settings::Flags::new(&shared_flags, builder),
         shared_flags,
     })
@@ -45,6 +50,10 @@ impl TargetIsa for Isa {
         "arm64"
     }
 
+    fn triple(&self) -> &Triple {
+        &self.triple
+    }
+
     fn flags(&self) -> &shared_settings::Flags {
         &self.shared_flags
     }

lib/codegen/src/isa/mod.rs

@@ -20,13 +20,18 @@
 //! appropriate for the requested ISA:
 //!
 //! ```
+//! # extern crate cretonne_codegen;
+//! # #[macro_use] extern crate target_lexicon;
+//! # fn main() {
 //! use cretonne_codegen::settings::{self, Configurable};
 //! use cretonne_codegen::isa;
+//! use std::str::FromStr;
+//! use target_lexicon::Triple;
 //!
 //! let shared_builder = settings::builder();
 //! let shared_flags = settings::Flags::new(shared_builder);
 //!
-//! match isa::lookup("riscv") {
+//! match isa::lookup(triple!("riscv32")) {
 //!     Err(_) => {
 //!         // The RISC-V target ISA is not available.
 //!     }
@@ -35,6 +40,7 @@
 //!         let isa = isa_builder.finish(shared_flags);
 //!     }
 //! }
+//! # }
 //! ```
 //!
 //! The configured target ISA trait object is a `Box<TargetIsa>` which can be used for multiple
@@ -55,6 +61,7 @@ use settings;
 use settings::CallConv;
 use std::boxed::Box;
 use std::fmt;
+use target_lexicon::{Architecture, Triple};
 use timing;
 
 #[cfg(build_riscv)]
@@ -80,51 +87,61 @@ mod stack;
 macro_rules! isa_builder {
     ($module:ident, $name:ident) => {{
         #[cfg($name)]
-        fn $name() -> Result<Builder, LookupError> {
-            Ok($module::isa_builder())
+        fn $name(triple: Triple) -> Result<Builder, LookupError> {
+            Ok($module::isa_builder(triple))
         };
         #[cfg(not($name))]
-        fn $name() -> Result<Builder, LookupError> {
+        fn $name(_triple: Triple) -> Result<Builder, LookupError> {
             Err(LookupError::Unsupported)
         }
-        $name()
+        $name
     }};
 }
 
 /// Look for a supported ISA with the given `name`.
 /// Return a builder that can create a corresponding `TargetIsa`.
-pub fn lookup(name: &str) -> Result<Builder, LookupError> {
-    match name {
-        "riscv" => isa_builder!(riscv, build_riscv),
-        "x86" => isa_builder!(x86, build_x86),
-        "arm32" => isa_builder!(arm32, build_arm32),
-        "arm64" => isa_builder!(arm64, build_arm64),
-        _ => Err(LookupError::Unknown),
+pub fn lookup(triple: Triple) -> Result<Builder, LookupError> {
+    match triple.architecture {
+        Architecture::Riscv32 | Architecture::Riscv64 => isa_builder!(riscv, build_riscv)(triple),
+        Architecture::I386 | Architecture::I586 | Architecture::I686 | Architecture::X86_64 => {
+            isa_builder!(x86, build_x86)(triple)
+        }
+        Architecture::Thumbv6m
+        | Architecture::Thumbv7em
+        | Architecture::Thumbv7m
+        | Architecture::Arm
+        | Architecture::Armv4t
+        | Architecture::Armv5te
+        | Architecture::Armv7
+        | Architecture::Armv7s => isa_builder!(arm32, build_arm32)(triple),
+        Architecture::Aarch64 => isa_builder!(arm64, build_arm64)(triple),
+        _ => Err(LookupError::Unsupported),
     }
 }
 
 /// Describes reason for target lookup failure
 #[derive(PartialEq, Eq, Copy, Clone, Debug)]
 pub enum LookupError {
-    /// Unknown Target
-    Unknown,
+    /// Support for this target was disabled in the current build.
+    SupportDisabled,
 
-    /// Target known but not built and thus not supported
+    /// Support for this target has not yet been implemented.
     Unsupported,
 }
 
 /// Builder for a `TargetIsa`.
 /// Modify the ISA-specific settings before creating the `TargetIsa` trait object with `finish`.
 pub struct Builder {
+    triple: Triple,
     setup: settings::Builder,
-    constructor: fn(settings::Flags, settings::Builder) -> Box<TargetIsa>,
+    constructor: fn(Triple, settings::Flags, settings::Builder) -> Box<TargetIsa>,
 }
 
 impl Builder {
     /// Combine the ISA-specific settings with the provided ISA-independent settings and allocate a
     /// fully configured `TargetIsa` trait object.
     pub fn finish(self, shared_flags: settings::Flags) -> Box<TargetIsa> {
-        (self.constructor)(shared_flags, self.setup)
+        (self.constructor)(self.triple, shared_flags, self.setup)
     }
 }
 
@@ -151,9 +168,17 @@ pub trait TargetIsa: fmt::Display {
     /// Get the name of this ISA.
     fn name(&self) -> &'static str;
 
+    /// Get the target triple that was used to make this trait object.
+    fn triple(&self) -> &Triple;
+
     /// Get the ISA-independent flags that were used to make this trait object.
     fn flags(&self) -> &settings::Flags;
 
+    /// Get the pointer type of this ISA.
+    fn pointer_type(&self) -> ir::Type {
+        ir::Type::int(u16::from(self.triple().pointer_width().unwrap().bits())).unwrap()
+    }
+
     /// Does the CPU implement scalar comparisons using a CPU flags register?
     fn uses_cpu_flags(&self) -> bool {
         false
@@ -252,7 +277,7 @@ pub trait TargetIsa: fmt::Display {
         use ir::stackslot::{StackOffset, StackSize};
         use stack_layout::layout_stack;
 
-        let word_size = if self.flags().is_64bit() { 8 } else { 4 };
+        let word_size = StackSize::from(self.triple().pointer_width().unwrap().bytes());
 
         // Account for the SpiderMonkey standard prologue pushes.
         if func.signature.call_conv == CallConv::Baldrdash {