MachInst backends: handle SourceLocs out-of-band, not in Insts.
In existing MachInst backends, many instructions -- any that can trap or result in a relocation -- carry `SourceLoc` values in order to propagate the location-in-original-source to use to describe resulting traps or relocation errors. This is quite tedious, and also error-prone: it is likely that the necessary plumbing will be missed in some cases, and in any case, it's unnecessarily verbose. This PR factors out the `SourceLoc` handling so that it is tracked during emission as part of the `EmitState`, and plumbed through automatically by the machine-independent framework. Instruction emission code that directly emits trap or relocation records can query the current location as necessary. Then we only need to ensure that memory references and trap instructions, at their (one) emission point rather than their (many) lowering/generation points, are wired up correctly. This does have the side-effect that some loads and stores that do not correspond directly to user code's heap accesses will have unnecessary but harmless trap metadata. For example, the load that fetches a code offset from a jump table will have a 'heap out of bounds' trap record attached to it; but because it is bounds-checked, and will never actually trap if the lowering is correct, this should be harmless. The simplicity improvement here seemed more worthwhile to me than plumbing through a "corresponds to user-level load/store" bit, because the latter is a bit complex when we allow for op merging. Closes #2290: though it does not implement a full "metadata" scheme as described in that issue, this seems simpler overall.
This commit is contained in:
Chris Fallin
@@ -420,7 +420,6 @@ pub struct CallInfo {
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pub dest: ExternalName,
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pub uses: Vec<Reg>,
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pub defs: Vec<Writable<Reg>>,
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pub loc: SourceLoc,
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pub opcode: Opcode,
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pub caller_callconv: CallConv,
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pub callee_callconv: CallConv,
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@@ -433,7 +432,6 @@ pub struct CallIndInfo {
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pub rn: Reg,
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pub uses: Vec<Reg>,
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pub defs: Vec<Writable<Reg>>,
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pub loc: SourceLoc,
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pub opcode: Opcode,
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pub caller_callconv: CallConv,
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pub callee_callconv: CallConv,
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@@ -524,68 +522,57 @@ pub enum Inst {
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ULoad8 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// A signed (sign-extending) 8-bit load.
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SLoad8 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// An unsigned (zero-extending) 16-bit load.
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ULoad16 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// A signed (sign-extending) 16-bit load.
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SLoad16 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// An unsigned (zero-extending) 32-bit load.
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ULoad32 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// A signed (sign-extending) 32-bit load.
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SLoad32 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// A 64-bit load.
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ULoad64 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// An 8-bit store.
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Store8 {
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rd: Reg,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// A 16-bit store.
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Store16 {
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rd: Reg,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// A 32-bit store.
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Store32 {
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rd: Reg,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// A 64-bit store.
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Store64 {
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rd: Reg,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// A store of a pair of registers.
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@@ -686,7 +673,6 @@ pub enum Inst {
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AtomicRMW {
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ty: Type, // I8, I16, I32 or I64
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op: inst_common::AtomicRmwOp,
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srcloc: Option<SourceLoc>,
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},
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/// Similar to AtomicRMW, a compare-and-swap operation implemented using a load-linked
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@@ -703,7 +689,6 @@ pub enum Inst {
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/// x24 (wr) scratch reg; value afterwards has no meaning
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AtomicCAS {
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ty: Type, // I8, I16, I32 or I64
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srcloc: Option<SourceLoc>,
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},
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/// Read `ty` bits from address `r_addr`, zero extend the loaded value to 64 bits and put it
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@@ -713,7 +698,6 @@ pub enum Inst {
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ty: Type, // I8, I16, I32 or I64
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r_data: Writable<Reg>,
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r_addr: Reg,
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srcloc: Option<SourceLoc>,
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},
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/// Write the lowest `ty` bits of `r_data` to address `r_addr`, with a memory fence
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@@ -723,7 +707,6 @@ pub enum Inst {
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ty: Type, // I8, I16, I32 or I64
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r_data: Reg,
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r_addr: Reg,
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srcloc: Option<SourceLoc>,
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},
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/// A memory fence. This must provide ordering to ensure that, at a minimum, neither loads
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@@ -798,37 +781,31 @@ pub enum Inst {
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FpuLoad32 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// Floating-point store, single-precision (32 bit).
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FpuStore32 {
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rd: Reg,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// Floating-point load, double-precision (64 bit).
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FpuLoad64 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// Floating-point store, double-precision (64 bit).
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FpuStore64 {
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rd: Reg,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// Floating-point/vector load, 128 bit.
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FpuLoad128 {
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rd: Writable<Reg>,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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/// Floating-point/vector store, 128 bit.
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FpuStore128 {
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rd: Reg,
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mem: AMode,
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srcloc: Option<SourceLoc>,
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},
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LoadFpuConst64 {
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@@ -1037,7 +1014,6 @@ pub enum Inst {
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rd: Writable<Reg>,
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rn: Reg,
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size: VectorSize,
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srcloc: Option<SourceLoc>,
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},
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/// Move to the NZCV flags (actually a `MSR NZCV, Xn` insn).
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@@ -1095,7 +1071,7 @@ pub enum Inst {
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/// of this condition in a branch that skips the trap instruction.)
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TrapIf {
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kind: CondBrKind,
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trap_info: (SourceLoc, TrapCode),
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trap_code: TrapCode,
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},
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/// An indirect branch through a register, augmented with set of all
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@@ -1111,7 +1087,7 @@ pub enum Inst {
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/// An instruction guaranteed to always be undefined and to trigger an illegal instruction at
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/// runtime.
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Udf {
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trap_info: (SourceLoc, TrapCode),
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trap_code: TrapCode,
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},
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/// Compute the address (using a PC-relative offset) of a memory location, using the `ADR`
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@@ -1146,7 +1122,6 @@ pub enum Inst {
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LoadExtName {
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rd: Writable<Reg>,
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name: Box<ExternalName>,
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srcloc: SourceLoc,
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offset: i64,
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},
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@@ -1457,47 +1432,22 @@ impl Inst {
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/// Generic constructor for a load (zero-extending where appropriate).
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pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type) -> Inst {
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match ty {
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B1 | B8 | I8 => Inst::ULoad8 {
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rd: into_reg,
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mem,
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srcloc: None,
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},
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B16 | I16 => Inst::ULoad16 {
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rd: into_reg,
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mem,
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srcloc: None,
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},
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B32 | I32 | R32 => Inst::ULoad32 {
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rd: into_reg,
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mem,
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srcloc: None,
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},
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B64 | I64 | R64 => Inst::ULoad64 {
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rd: into_reg,
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mem,
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srcloc: None,
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},
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F32 => Inst::FpuLoad32 {
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rd: into_reg,
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mem,
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srcloc: None,
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},
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F64 => Inst::FpuLoad64 {
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rd: into_reg,
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mem,
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srcloc: None,
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},
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B1 | B8 | I8 => Inst::ULoad8 { rd: into_reg, mem },
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B16 | I16 => Inst::ULoad16 { rd: into_reg, mem },
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B32 | I32 | R32 => Inst::ULoad32 { rd: into_reg, mem },
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B64 | I64 | R64 => Inst::ULoad64 { rd: into_reg, mem },
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F32 => Inst::FpuLoad32 { rd: into_reg, mem },
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F64 => Inst::FpuLoad64 { rd: into_reg, mem },
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_ => {
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if ty.is_vector() {
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let bits = ty_bits(ty);
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let rd = into_reg;
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let srcloc = None;
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if bits == 128 {
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Inst::FpuLoad128 { rd, mem, srcloc }
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Inst::FpuLoad128 { rd, mem }
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} else {
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assert_eq!(bits, 64);
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Inst::FpuLoad64 { rd, mem, srcloc }
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Inst::FpuLoad64 { rd, mem }
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}
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} else {
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unimplemented!("gen_load({})", ty);
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@@ -1509,47 +1459,22 @@ impl Inst {
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/// Generic constructor for a store.
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pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type) -> Inst {
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match ty {
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B1 | B8 | I8 => Inst::Store8 {
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rd: from_reg,
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mem,
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srcloc: None,
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},
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B16 | I16 => Inst::Store16 {
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rd: from_reg,
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mem,
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srcloc: None,
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},
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B32 | I32 | R32 => Inst::Store32 {
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rd: from_reg,
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mem,
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srcloc: None,
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},
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B64 | I64 | R64 => Inst::Store64 {
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rd: from_reg,
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mem,
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srcloc: None,
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},
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F32 => Inst::FpuStore32 {
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rd: from_reg,
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mem,
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srcloc: None,
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},
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F64 => Inst::FpuStore64 {
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rd: from_reg,
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mem,
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srcloc: None,
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},
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B1 | B8 | I8 => Inst::Store8 { rd: from_reg, mem },
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B16 | I16 => Inst::Store16 { rd: from_reg, mem },
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B32 | I32 | R32 => Inst::Store32 { rd: from_reg, mem },
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B64 | I64 | R64 => Inst::Store64 { rd: from_reg, mem },
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F32 => Inst::FpuStore32 { rd: from_reg, mem },
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F64 => Inst::FpuStore64 { rd: from_reg, mem },
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_ => {
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if ty.is_vector() {
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let bits = ty_bits(ty);
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let rd = from_reg;
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let srcloc = None;
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if bits == 128 {
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Inst::FpuStore128 { rd, mem, srcloc }
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Inst::FpuStore128 { rd, mem }
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} else {
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assert_eq!(bits, 64);
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Inst::FpuStore64 { rd, mem, srcloc }
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Inst::FpuStore64 { rd, mem }
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}
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} else {
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unimplemented!("gen_store({})", ty);
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@@ -3024,37 +2949,30 @@ impl Inst {
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&Inst::ULoad8 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::SLoad8 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::ULoad16 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::SLoad16 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::ULoad32 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::SLoad32 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::ULoad64 {
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rd,
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ref mem,
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srcloc: _srcloc,
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..
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} => {
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let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
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@@ -3087,22 +3005,18 @@ impl Inst {
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&Inst::Store8 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::Store16 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::Store32 {
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rd,
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ref mem,
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srcloc: _srcloc,
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}
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| &Inst::Store64 {
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rd,
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ref mem,
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srcloc: _srcloc,
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..
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} => {
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let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
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@@ -3841,7 +3755,6 @@ impl Inst {
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rd,
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ref name,
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offset,
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srcloc: _srcloc,
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} => {
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let rd = rd.show_rru(mb_rru);
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format!("ldr {}, 8 ; b 12 ; data {:?} + {}", rd, name, offset)
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