From 4dce51096d29397131fde4671a6f1d322e28c6f8 Mon Sep 17 00:00:00 2001 From: Chris Fallin Date: Tue, 10 Nov 2020 14:37:11 -0800 Subject: [PATCH] MachInst backends: handle SourceLocs out-of-band, not in Insts. In existing MachInst backends, many instructions -- any that can trap or result in a relocation -- carry `SourceLoc` values in order to propagate the location-in-original-source to use to describe resulting traps or relocation errors. This is quite tedious, and also error-prone: it is likely that the necessary plumbing will be missed in some cases, and in any case, it's unnecessarily verbose. This PR factors out the `SourceLoc` handling so that it is tracked during emission as part of the `EmitState`, and plumbed through automatically by the machine-independent framework. Instruction emission code that directly emits trap or relocation records can query the current location as necessary. Then we only need to ensure that memory references and trap instructions, at their (one) emission point rather than their (many) lowering/generation points, are wired up correctly. This does have the side-effect that some loads and stores that do not correspond directly to user code's heap accesses will have unnecessary but harmless trap metadata. For example, the load that fetches a code offset from a jump table will have a 'heap out of bounds' trap record attached to it; but because it is bounds-checked, and will never actually trap if the lowering is correct, this should be harmless. The simplicity improvement here seemed more worthwhile to me than plumbing through a "corresponds to user-level load/store" bit, because the latter is a bit complex when we allow for op merging. Closes #2290: though it does not implement a full "metadata" scheme as described in that issue, this seems simpler overall. --- cranelift/codegen/src/isa/aarch64/abi.rs | 10 +- .../codegen/src/isa/aarch64/inst/emit.rs | 191 ++--- .../src/isa/aarch64/inst/emit_tests.rs | 109 +-- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 123 +-- .../codegen/src/isa/aarch64/lower_inst.rs | 147 ++-- cranelift/codegen/src/isa/arm32/abi.rs | 8 +- cranelift/codegen/src/isa/arm32/inst/emit.rs | 40 +- .../codegen/src/isa/arm32/inst/emit_tests.rs | 48 +- cranelift/codegen/src/isa/arm32/inst/mod.rs | 14 +- cranelift/codegen/src/isa/arm32/lower_inst.rs | 29 +- cranelift/codegen/src/isa/x64/abi.rs | 26 +- cranelift/codegen/src/isa/x64/inst/emit.rs | 366 +++++---- .../codegen/src/isa/x64/inst/emit_tests.rs | 744 +++++++----------- cranelift/codegen/src/isa/x64/inst/mod.rs | 237 ++---- cranelift/codegen/src/isa/x64/lower.rs | 451 +++-------- cranelift/codegen/src/machinst/abi_impl.rs | 10 +- cranelift/codegen/src/machinst/buffer.rs | 4 +- cranelift/codegen/src/machinst/mod.rs | 5 +- cranelift/codegen/src/machinst/vcode.rs | 1 + 19 files changed, 849 insertions(+), 1714 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs index ba9abc5cb7..90debad44e 100644 --- a/cranelift/codegen/src/isa/aarch64/abi.rs +++ b/cranelift/codegen/src/isa/aarch64/abi.rs @@ -3,7 +3,6 @@ use crate::ir; use crate::ir::types; use crate::ir::types::*; -use crate::ir::SourceLoc; use crate::isa; use crate::isa::aarch64::{inst::EmitState, inst::*}; use crate::machinst::*; @@ -380,7 +379,7 @@ impl ABIMachineSpec for AArch64MachineDeps { extendop: ExtendOp::UXTX, }); insts.push(Inst::TrapIf { - trap_info: (ir::SourceLoc::default(), ir::TrapCode::StackOverflow), + trap_code: ir::TrapCode::StackOverflow, // Here `Lo` == "less than" when interpreting the two // operands as unsigned integers. kind: CondBrKind::Cond(Cond::Lo), @@ -554,7 +553,6 @@ impl ABIMachineSpec for AArch64MachineDeps { stack_reg(), SImm9::maybe_from_i64((vec_offset + (i * 16)) as i64).unwrap(), ), - srcloc: None, }); } @@ -603,7 +601,6 @@ impl ABIMachineSpec for AArch64MachineDeps { stack_reg(), SImm9::maybe_from_i64(((i * 16) + int_save_bytes) as i64).unwrap(), ), - srcloc: None, }); } @@ -634,7 +631,6 @@ impl ABIMachineSpec for AArch64MachineDeps { dest: &CallDest, uses: Vec, defs: Vec>, - loc: SourceLoc, opcode: ir::Opcode, tmp: Writable, callee_conv: isa::CallConv, @@ -649,7 +645,6 @@ impl ABIMachineSpec for AArch64MachineDeps { dest: name.clone(), uses, defs, - loc, opcode, caller_callconv: caller_conv, callee_callconv: callee_conv, @@ -663,7 +658,6 @@ impl ABIMachineSpec for AArch64MachineDeps { rd: tmp, name: Box::new(name.clone()), offset: 0, - srcloc: loc, }, )); insts.push(( @@ -673,7 +667,6 @@ impl ABIMachineSpec for AArch64MachineDeps { rn: tmp.to_reg(), uses, defs, - loc, opcode, caller_callconv: caller_conv, callee_callconv: callee_conv, @@ -688,7 +681,6 @@ impl ABIMachineSpec for AArch64MachineDeps { rn: *reg, uses, defs, - loc, opcode, caller_callconv: caller_conv, callee_callconv: callee_conv, diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index 5aad8f1c30..2d7c02f215 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -462,6 +462,8 @@ pub struct EmitState { pub(crate) nominal_sp_to_fp: i64, /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`. stack_map: Option, + /// Current source-code location corresponding to instruction to be emitted. + cur_srcloc: SourceLoc, } impl MachInstEmitState for EmitState { @@ -470,12 +472,17 @@ impl MachInstEmitState for EmitState { virtual_sp_offset: 0, nominal_sp_to_fp: abi.frame_size() as i64, stack_map: None, + cur_srcloc: SourceLoc::default(), } } fn pre_safepoint(&mut self, stack_map: StackMap) { self.stack_map = Some(stack_map); } + + fn pre_sourceloc(&mut self, srcloc: SourceLoc) { + self.cur_srcloc = srcloc; + } } impl EmitState { @@ -486,6 +493,10 @@ impl EmitState { fn clear_post_insn(&mut self) { self.stack_map = None; } + + fn cur_srcloc(&self) -> SourceLoc { + self.cur_srcloc + } } /// Constant state used during function compilation. @@ -730,57 +741,16 @@ impl MachInstEmit for Inst { sink.put4(enc_bit_rr(size, op1, op2, rn, rd)) } - &Inst::ULoad8 { - rd, - ref mem, - srcloc, - } - | &Inst::SLoad8 { - rd, - ref mem, - srcloc, - } - | &Inst::ULoad16 { - rd, - ref mem, - srcloc, - } - | &Inst::SLoad16 { - rd, - ref mem, - srcloc, - } - | &Inst::ULoad32 { - rd, - ref mem, - srcloc, - } - | &Inst::SLoad32 { - rd, - ref mem, - srcloc, - } - | &Inst::ULoad64 { - rd, - ref mem, - srcloc, - .. - } - | &Inst::FpuLoad32 { - rd, - ref mem, - srcloc, - } - | &Inst::FpuLoad64 { - rd, - ref mem, - srcloc, - } - | &Inst::FpuLoad128 { - rd, - ref mem, - srcloc, - } => { + &Inst::ULoad8 { rd, ref mem } + | &Inst::SLoad8 { rd, ref mem } + | &Inst::ULoad16 { rd, ref mem } + | &Inst::SLoad16 { rd, ref mem } + | &Inst::ULoad32 { rd, ref mem } + | &Inst::SLoad32 { rd, ref mem } + | &Inst::ULoad64 { rd, ref mem, .. } + | &Inst::FpuLoad32 { rd, ref mem } + | &Inst::FpuLoad64 { rd, ref mem } + | &Inst::FpuLoad128 { rd, ref mem } => { let (mem_insts, mem) = mem_finalize(sink.cur_offset(), mem, state); for inst in mem_insts.into_iter() { @@ -807,7 +777,8 @@ impl MachInstEmit for Inst { _ => unreachable!(), }; - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { // Register the offset at which the actual load instruction starts. sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } @@ -890,42 +861,13 @@ impl MachInstEmit for Inst { } } - &Inst::Store8 { - rd, - ref mem, - srcloc, - } - | &Inst::Store16 { - rd, - ref mem, - srcloc, - } - | &Inst::Store32 { - rd, - ref mem, - srcloc, - } - | &Inst::Store64 { - rd, - ref mem, - srcloc, - .. - } - | &Inst::FpuStore32 { - rd, - ref mem, - srcloc, - } - | &Inst::FpuStore64 { - rd, - ref mem, - srcloc, - } - | &Inst::FpuStore128 { - rd, - ref mem, - srcloc, - } => { + &Inst::Store8 { rd, ref mem } + | &Inst::Store16 { rd, ref mem } + | &Inst::Store32 { rd, ref mem } + | &Inst::Store64 { rd, ref mem, .. } + | &Inst::FpuStore32 { rd, ref mem } + | &Inst::FpuStore64 { rd, ref mem } + | &Inst::FpuStore128 { rd, ref mem } => { let (mem_insts, mem) = mem_finalize(sink.cur_offset(), mem, state); for inst in mem_insts.into_iter() { @@ -943,7 +885,8 @@ impl MachInstEmit for Inst { _ => unreachable!(), }; - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { // Register the offset at which the actual load instruction starts. sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } @@ -1086,7 +1029,7 @@ impl MachInstEmit for Inst { } => { sink.put4(enc_ccmp_imm(size, rn, imm, nzcv, cond)); } - &Inst::AtomicRMW { ty, op, srcloc } => { + &Inst::AtomicRMW { ty, op } => { /* Emit this: dmb ish again: @@ -1124,7 +1067,8 @@ impl MachInstEmit for Inst { // again: sink.bind_label(again_label); - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } sink.put4(enc_ldxr(ty, x27wr, x25)); // ldxr x27, [x25] @@ -1145,7 +1089,8 @@ impl MachInstEmit for Inst { sink.put4(enc_arith_rrr(bits_31_21, 0b000000, x28wr, x27, x26)); } - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } sink.put4(enc_stxr(ty, x24wr, x28, x25)); // stxr w24, x28, [x25] @@ -1162,7 +1107,7 @@ impl MachInstEmit for Inst { sink.put4(enc_dmb_ish()); // dmb ish } - &Inst::AtomicCAS { ty, srcloc } => { + &Inst::AtomicCAS { ty } => { /* Emit this: dmb ish again: @@ -1195,7 +1140,8 @@ impl MachInstEmit for Inst { // again: sink.bind_label(again_label); - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } sink.put4(enc_ldxr(ty, x27wr, x25)); // ldxr x27, [x25] @@ -1230,7 +1176,8 @@ impl MachInstEmit for Inst { )); sink.use_label_at_offset(br_out_offset, out_label, LabelUse::Branch19); - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } sink.put4(enc_stxr(ty, x24wr, x28, x25)); // stxr w24, x28, [x25] @@ -1249,12 +1196,7 @@ impl MachInstEmit for Inst { sink.bind_label(out_label); sink.put4(enc_dmb_ish()); // dmb ish } - &Inst::AtomicLoad { - ty, - r_data, - r_addr, - srcloc, - } => { + &Inst::AtomicLoad { ty, r_data, r_addr } => { let op = match ty { I8 => 0b0011100001, I16 => 0b0111100001, @@ -1264,7 +1206,8 @@ impl MachInstEmit for Inst { }; sink.put4(enc_dmb_ish()); // dmb ish - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } let uimm12scaled_zero = UImm12Scaled::zero(I8 /*irrelevant*/); @@ -1275,12 +1218,7 @@ impl MachInstEmit for Inst { r_data.to_reg(), )); } - &Inst::AtomicStore { - ty, - r_data, - r_addr, - srcloc, - } => { + &Inst::AtomicStore { ty, r_data, r_addr } => { let op = match ty { I8 => 0b0011100000, I16 => 0b0111100000, @@ -1289,7 +1227,8 @@ impl MachInstEmit for Inst { _ => unreachable!(), }; - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } let uimm12scaled_zero = UImm12Scaled::zero(I8 /*irrelevant*/); @@ -1607,7 +1546,6 @@ impl MachInstEmit for Inst { let inst = Inst::FpuLoad64 { rd, mem: AMode::Label(MemLabel::PCRel(8)), - srcloc: None, }; inst.emit(sink, emit_info, state); let inst = Inst::Jump { @@ -1620,7 +1558,6 @@ impl MachInstEmit for Inst { let inst = Inst::FpuLoad128 { rd, mem: AMode::Label(MemLabel::PCRel(8)), - srcloc: None, }; inst.emit(sink, emit_info, state); let inst = Inst::Jump { @@ -1961,15 +1898,11 @@ impl MachInstEmit for Inst { }; sink.put4(enc_vec_rrr(top11, rm, bit15_10, rn, rd)); } - &Inst::VecLoadReplicate { - rd, - rn, - size, - srcloc, - } => { + &Inst::VecLoadReplicate { rd, rn, size } => { let (q, size) = size.enc_size(); - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { // Register the offset at which the actual load instruction starts. sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } @@ -2073,10 +2006,11 @@ impl MachInstEmit for Inst { if let Some(s) = state.take_stack_map() { sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s); } - sink.add_reloc(info.loc, Reloc::Arm64Call, &info.dest, 0); + let loc = state.cur_srcloc(); + sink.add_reloc(loc, Reloc::Arm64Call, &info.dest, 0); sink.put4(enc_jump26(0b100101, 0)); if info.opcode.is_call() { - sink.add_call_site(info.loc, info.opcode); + sink.add_call_site(loc, info.opcode); } } &Inst::CallInd { ref info } => { @@ -2084,8 +2018,9 @@ impl MachInstEmit for Inst { sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s); } sink.put4(0b1101011_0001_11111_000000_00000_00000 | (machreg_to_gpr(info.rn) << 5)); + let loc = state.cur_srcloc(); if info.opcode.is_call() { - sink.add_call_site(info.loc, info.opcode); + sink.add_call_site(loc, info.opcode); } } &Inst::CondBr { @@ -2110,7 +2045,7 @@ impl MachInstEmit for Inst { } sink.put4(enc_jump26(0b000101, not_taken.as_offset26_or_zero())); } - &Inst::TrapIf { kind, trap_info } => { + &Inst::TrapIf { kind, trap_code } => { // condbr KIND, LABEL let off = sink.cur_offset(); let label = sink.get_label(); @@ -2120,7 +2055,7 @@ impl MachInstEmit for Inst { )); sink.use_label_at_offset(off, label, LabelUse::Branch19); // udf - let trap = Inst::Udf { trap_info }; + let trap = Inst::Udf { trap_code }; trap.emit(sink, emit_info, state); // LABEL: sink.bind_label(label); @@ -2135,9 +2070,9 @@ impl MachInstEmit for Inst { &Inst::Brk => { sink.put4(0xd4200000); } - &Inst::Udf { trap_info } => { - let (srcloc, code) = trap_info; - sink.add_trap(srcloc, code); + &Inst::Udf { trap_code } => { + let srcloc = state.cur_srcloc(); + sink.add_trap(srcloc, trap_code); if let Some(s) = state.take_stack_map() { sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s); } @@ -2192,7 +2127,6 @@ impl MachInstEmit for Inst { I32, ExtendOp::UXTW, ), - srcloc: None, // can't cause a user trap. }; inst.emit(sink, emit_info, state); // Add base of jump table to jump-table-sourced block offset @@ -2235,18 +2169,17 @@ impl MachInstEmit for Inst { rd, ref name, offset, - srcloc, } => { let inst = Inst::ULoad64 { rd, mem: AMode::Label(MemLabel::PCRel(8)), - srcloc: None, // can't cause a user trap. }; inst.emit(sink, emit_info, state); let inst = Inst::Jump { dest: BranchTarget::ResolvedOffset(12), }; inst.emit(sink, emit_info, state); + let srcloc = state.cur_srcloc(); sink.add_reloc(srcloc, Reloc::Abs8, name, offset); if emit_info.flags().emit_all_ones_funcaddrs() { sink.put8(u64::max_value()); diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index 4c73244b92..ca1eee46dc 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -1079,7 +1079,6 @@ fn test_aarch64_binemit() { Inst::ULoad8 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "41004038", "ldurb w1, [x2]", @@ -1088,7 +1087,6 @@ fn test_aarch64_binemit() { Inst::ULoad8 { rd: writable_xreg(1), mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::zero(I8)), - srcloc: None, }, "41004039", "ldrb w1, [x2]", @@ -1097,7 +1095,6 @@ fn test_aarch64_binemit() { Inst::ULoad8 { rd: writable_xreg(1), mem: AMode::RegReg(xreg(2), xreg(5)), - srcloc: None, }, "41686538", "ldrb w1, [x2, x5]", @@ -1106,7 +1103,6 @@ fn test_aarch64_binemit() { Inst::SLoad8 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "41008038", "ldursb x1, [x2]", @@ -1115,7 +1111,6 @@ fn test_aarch64_binemit() { Inst::SLoad8 { rd: writable_xreg(1), mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(63, I8).unwrap()), - srcloc: None, }, "41FC8039", "ldrsb x1, [x2, #63]", @@ -1124,7 +1119,6 @@ fn test_aarch64_binemit() { Inst::SLoad8 { rd: writable_xreg(1), mem: AMode::RegReg(xreg(2), xreg(5)), - srcloc: None, }, "4168A538", "ldrsb x1, [x2, x5]", @@ -1133,7 +1127,6 @@ fn test_aarch64_binemit() { Inst::ULoad16 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(5).unwrap()), - srcloc: None, }, "41504078", "ldurh w1, [x2, #5]", @@ -1142,7 +1135,6 @@ fn test_aarch64_binemit() { Inst::ULoad16 { rd: writable_xreg(1), mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(8, I16).unwrap()), - srcloc: None, }, "41104079", "ldrh w1, [x2, #8]", @@ -1151,7 +1143,6 @@ fn test_aarch64_binemit() { Inst::ULoad16 { rd: writable_xreg(1), mem: AMode::RegScaled(xreg(2), xreg(3), I16), - srcloc: None, }, "41786378", "ldrh w1, [x2, x3, LSL #1]", @@ -1160,7 +1151,6 @@ fn test_aarch64_binemit() { Inst::SLoad16 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "41008078", "ldursh x1, [x2]", @@ -1169,7 +1159,6 @@ fn test_aarch64_binemit() { Inst::SLoad16 { rd: writable_xreg(28), mem: AMode::UnsignedOffset(xreg(20), UImm12Scaled::maybe_from_i64(24, I16).unwrap()), - srcloc: None, }, "9C328079", "ldrsh x28, [x20, #24]", @@ -1178,7 +1167,6 @@ fn test_aarch64_binemit() { Inst::SLoad16 { rd: writable_xreg(28), mem: AMode::RegScaled(xreg(20), xreg(20), I16), - srcloc: None, }, "9C7AB478", "ldrsh x28, [x20, x20, LSL #1]", @@ -1187,7 +1175,6 @@ fn test_aarch64_binemit() { Inst::ULoad32 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "410040B8", "ldur w1, [x2]", @@ -1196,7 +1183,6 @@ fn test_aarch64_binemit() { Inst::ULoad32 { rd: writable_xreg(12), mem: AMode::UnsignedOffset(xreg(0), UImm12Scaled::maybe_from_i64(204, I32).unwrap()), - srcloc: None, }, "0CCC40B9", "ldr w12, [x0, #204]", @@ -1205,7 +1191,6 @@ fn test_aarch64_binemit() { Inst::ULoad32 { rd: writable_xreg(1), mem: AMode::RegScaled(xreg(2), xreg(12), I32), - srcloc: None, }, "41786CB8", "ldr w1, [x2, x12, LSL #2]", @@ -1214,7 +1199,6 @@ fn test_aarch64_binemit() { Inst::SLoad32 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "410080B8", "ldursw x1, [x2]", @@ -1223,7 +1207,6 @@ fn test_aarch64_binemit() { Inst::SLoad32 { rd: writable_xreg(12), mem: AMode::UnsignedOffset(xreg(1), UImm12Scaled::maybe_from_i64(16380, I32).unwrap()), - srcloc: None, }, "2CFCBFB9", "ldrsw x12, [x1, #16380]", @@ -1232,7 +1215,6 @@ fn test_aarch64_binemit() { Inst::SLoad32 { rd: writable_xreg(1), mem: AMode::RegScaled(xreg(5), xreg(1), I32), - srcloc: None, }, "A178A1B8", "ldrsw x1, [x5, x1, LSL #2]", @@ -1241,7 +1223,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "410040F8", "ldur x1, [x2]", @@ -1250,7 +1231,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(-256).unwrap()), - srcloc: None, }, "410050F8", "ldur x1, [x2, #-256]", @@ -1259,7 +1239,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(255).unwrap()), - srcloc: None, }, "41F04FF8", "ldur x1, [x2, #255]", @@ -1268,7 +1247,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(32760, I64).unwrap()), - srcloc: None, }, "41FC7FF9", "ldr x1, [x2, #32760]", @@ -1277,7 +1255,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::RegReg(xreg(2), xreg(3)), - srcloc: None, }, "416863F8", "ldr x1, [x2, x3]", @@ -1286,7 +1263,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::RegScaled(xreg(2), xreg(3), I64), - srcloc: None, }, "417863F8", "ldr x1, [x2, x3, LSL #3]", @@ -1295,7 +1271,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::RegScaledExtended(xreg(2), xreg(3), I64, ExtendOp::SXTW), - srcloc: None, }, "41D863F8", "ldr x1, [x2, w3, SXTW #3]", @@ -1304,7 +1279,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::RegExtended(xreg(2), xreg(3), ExtendOp::SXTW), - srcloc: None, }, "41C863F8", "ldr x1, [x2, w3, SXTW]", @@ -1313,7 +1287,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::Label(MemLabel::PCRel(64)), - srcloc: None, }, "01020058", "ldr x1, pc+64", @@ -1322,7 +1295,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::PreIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()), - srcloc: None, }, "410C41F8", "ldr x1, [x2, #16]!", @@ -1331,7 +1303,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::PostIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()), - srcloc: None, }, "410441F8", "ldr x1, [x2], #16", @@ -1340,7 +1311,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::FPOffset(32768, I8), - srcloc: None, }, "100090D2B063308B010240F9", "movz x16, #32768 ; add x16, fp, x16, UXTX ; ldr x1, [x16]", @@ -1349,7 +1319,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::FPOffset(-32768, I8), - srcloc: None, }, "F0FF8F92B063308B010240F9", "movn x16, #32767 ; add x16, fp, x16, UXTX ; ldr x1, [x16]", @@ -1358,7 +1327,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::FPOffset(1048576, I8), // 2^20 - srcloc: None, }, "1002A0D2B063308B010240F9", "movz x16, #16, LSL #16 ; add x16, fp, x16, UXTX ; ldr x1, [x16]", @@ -1367,7 +1335,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::FPOffset(1048576 + 1, I8), // 2^20 + 1 - srcloc: None, }, "300080521002A072B063308B010240F9", "movz w16, #1 ; movk w16, #16, LSL #16 ; add x16, fp, x16, UXTX ; ldr x1, [x16]", @@ -1377,7 +1344,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::RegOffset(xreg(7), 8, I64), - srcloc: None, }, "E18040F8", "ldur x1, [x7, #8]", @@ -1387,7 +1353,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::RegOffset(xreg(7), 1024, I64), - srcloc: None, }, "E10042F9", "ldr x1, [x7, #1024]", @@ -1397,7 +1362,6 @@ fn test_aarch64_binemit() { Inst::ULoad64 { rd: writable_xreg(1), mem: AMode::RegOffset(xreg(7), 1048576, I64), - srcloc: None, }, "1002A0D2F060308B010240F9", "movz x16, #16, LSL #16 ; add x16, x7, x16, UXTX ; ldr x1, [x16]", @@ -1407,7 +1371,6 @@ fn test_aarch64_binemit() { Inst::Store8 { rd: xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "41000038", "sturb w1, [x2]", @@ -1416,7 +1379,6 @@ fn test_aarch64_binemit() { Inst::Store8 { rd: xreg(1), mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(4095, I8).unwrap()), - srcloc: None, }, "41FC3F39", "strb w1, [x2, #4095]", @@ -1425,7 +1387,6 @@ fn test_aarch64_binemit() { Inst::Store16 { rd: xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "41000078", "sturh w1, [x2]", @@ -1434,7 +1395,6 @@ fn test_aarch64_binemit() { Inst::Store16 { rd: xreg(1), mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(8190, I16).unwrap()), - srcloc: None, }, "41FC3F79", "strh w1, [x2, #8190]", @@ -1443,7 +1403,6 @@ fn test_aarch64_binemit() { Inst::Store32 { rd: xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "410000B8", "stur w1, [x2]", @@ -1452,7 +1411,6 @@ fn test_aarch64_binemit() { Inst::Store32 { rd: xreg(1), mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(16380, I32).unwrap()), - srcloc: None, }, "41FC3FB9", "str w1, [x2, #16380]", @@ -1461,7 +1419,6 @@ fn test_aarch64_binemit() { Inst::Store64 { rd: xreg(1), mem: AMode::Unscaled(xreg(2), SImm9::zero()), - srcloc: None, }, "410000F8", "stur x1, [x2]", @@ -1470,7 +1427,6 @@ fn test_aarch64_binemit() { Inst::Store64 { rd: xreg(1), mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(32760, I64).unwrap()), - srcloc: None, }, "41FC3FF9", "str x1, [x2, #32760]", @@ -1479,7 +1435,6 @@ fn test_aarch64_binemit() { Inst::Store64 { rd: xreg(1), mem: AMode::RegReg(xreg(2), xreg(3)), - srcloc: None, }, "416823F8", "str x1, [x2, x3]", @@ -1488,7 +1443,6 @@ fn test_aarch64_binemit() { Inst::Store64 { rd: xreg(1), mem: AMode::RegScaled(xreg(2), xreg(3), I64), - srcloc: None, }, "417823F8", "str x1, [x2, x3, LSL #3]", @@ -1497,7 +1451,6 @@ fn test_aarch64_binemit() { Inst::Store64 { rd: xreg(1), mem: AMode::RegScaledExtended(xreg(2), xreg(3), I64, ExtendOp::UXTW), - srcloc: None, }, "415823F8", "str x1, [x2, w3, UXTW #3]", @@ -1506,7 +1459,6 @@ fn test_aarch64_binemit() { Inst::Store64 { rd: xreg(1), mem: AMode::RegExtended(xreg(2), xreg(3), ExtendOp::UXTW), - srcloc: None, }, "414823F8", "str x1, [x2, w3, UXTW]", @@ -1515,7 +1467,6 @@ fn test_aarch64_binemit() { Inst::Store64 { rd: xreg(1), mem: AMode::PreIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()), - srcloc: None, }, "410C01F8", "str x1, [x2, #16]!", @@ -1524,7 +1475,6 @@ fn test_aarch64_binemit() { Inst::Store64 { rd: xreg(1), mem: AMode::PostIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()), - srcloc: None, }, "410401F8", "str x1, [x2], #16", @@ -3911,7 +3861,7 @@ fn test_aarch64_binemit() { Inst::VecLoadReplicate { rd: writable_vreg(31), rn: xreg(0), - srcloc: None, + size: VectorSize::Size64x2, }, "1FCC404D", @@ -3922,7 +3872,7 @@ fn test_aarch64_binemit() { Inst::VecLoadReplicate { rd: writable_vreg(0), rn: xreg(25), - srcloc: None, + size: VectorSize::Size8x8, }, "20C3400D", @@ -4050,7 +4000,7 @@ fn test_aarch64_binemit() { insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::NotZero(xreg(8)), }, "480000B40000A0D4", @@ -4058,7 +4008,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Zero(xreg(8)), }, "480000B50000A0D4", @@ -4066,7 +4016,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Ne), }, "400000540000A0D4", @@ -4074,7 +4024,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Eq), }, "410000540000A0D4", @@ -4082,7 +4032,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Lo), }, "420000540000A0D4", @@ -4090,7 +4040,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Hs), }, "430000540000A0D4", @@ -4098,7 +4048,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Pl), }, "440000540000A0D4", @@ -4106,7 +4056,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Mi), }, "450000540000A0D4", @@ -4114,7 +4064,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Vc), }, "460000540000A0D4", @@ -4122,7 +4072,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Vs), }, "470000540000A0D4", @@ -4130,7 +4080,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Ls), }, "480000540000A0D4", @@ -4138,7 +4088,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Hi), }, "490000540000A0D4", @@ -4146,7 +4096,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Lt), }, "4A0000540000A0D4", @@ -4154,7 +4104,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Ge), }, "4B0000540000A0D4", @@ -4162,7 +4112,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Le), }, "4C0000540000A0D4", @@ -4170,7 +4120,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Gt), }, "4D0000540000A0D4", @@ -4178,7 +4128,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Nv), }, "4E0000540000A0D4", @@ -4186,7 +4136,7 @@ fn test_aarch64_binemit() { )); insns.push(( Inst::TrapIf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, kind: CondBrKind::Cond(Cond::Al), }, "4F0000540000A0D4", @@ -4209,7 +4159,6 @@ fn test_aarch64_binemit() { dest: ExternalName::testcase("test0"), uses: Vec::new(), defs: Vec::new(), - loc: SourceLoc::default(), opcode: Opcode::Call, caller_callconv: CallConv::SystemV, callee_callconv: CallConv::SystemV, @@ -4225,7 +4174,6 @@ fn test_aarch64_binemit() { rn: xreg(10), uses: Vec::new(), defs: Vec::new(), - loc: SourceLoc::default(), opcode: Opcode::CallIndirect, caller_callconv: CallConv::SystemV, callee_callconv: CallConv::SystemV, @@ -4797,7 +4745,6 @@ fn test_aarch64_binemit() { Inst::FpuLoad32 { rd: writable_vreg(16), mem: AMode::RegScaled(xreg(8), xreg(9), F32), - srcloc: None, }, "107969BC", "ldr s16, [x8, x9, LSL #2]", @@ -4807,7 +4754,6 @@ fn test_aarch64_binemit() { Inst::FpuLoad64 { rd: writable_vreg(16), mem: AMode::RegScaled(xreg(8), xreg(9), F64), - srcloc: None, }, "107969FC", "ldr d16, [x8, x9, LSL #3]", @@ -4817,7 +4763,6 @@ fn test_aarch64_binemit() { Inst::FpuLoad128 { rd: writable_vreg(16), mem: AMode::RegScaled(xreg(8), xreg(9), I128), - srcloc: None, }, "1079E93C", "ldr q16, [x8, x9, LSL #4]", @@ -4827,7 +4772,6 @@ fn test_aarch64_binemit() { Inst::FpuLoad32 { rd: writable_vreg(16), mem: AMode::Label(MemLabel::PCRel(8)), - srcloc: None, }, "5000001C", "ldr s16, pc+8", @@ -4837,7 +4781,6 @@ fn test_aarch64_binemit() { Inst::FpuLoad64 { rd: writable_vreg(16), mem: AMode::Label(MemLabel::PCRel(8)), - srcloc: None, }, "5000005C", "ldr d16, pc+8", @@ -4847,7 +4790,6 @@ fn test_aarch64_binemit() { Inst::FpuLoad128 { rd: writable_vreg(16), mem: AMode::Label(MemLabel::PCRel(8)), - srcloc: None, }, "5000009C", "ldr q16, pc+8", @@ -4857,7 +4799,6 @@ fn test_aarch64_binemit() { Inst::FpuStore32 { rd: vreg(16), mem: AMode::RegScaled(xreg(8), xreg(9), F32), - srcloc: None, }, "107929BC", "str s16, [x8, x9, LSL #2]", @@ -4867,7 +4808,6 @@ fn test_aarch64_binemit() { Inst::FpuStore64 { rd: vreg(16), mem: AMode::RegScaled(xreg(8), xreg(9), F64), - srcloc: None, }, "107929FC", "str d16, [x8, x9, LSL #3]", @@ -4877,7 +4817,6 @@ fn test_aarch64_binemit() { Inst::FpuStore128 { rd: vreg(16), mem: AMode::RegScaled(xreg(8), xreg(9), I128), - srcloc: None, }, "1079A93C", "str q16, [x8, x9, LSL #4]", @@ -5000,7 +4939,6 @@ fn test_aarch64_binemit() { Inst::AtomicRMW { ty: I16, op: inst_common::AtomicRmwOp::Xor, - srcloc: None, }, "BF3B03D53B7F5F487C031ACA3C7F1848B8FFFFB5BF3B03D5", "atomically { 16_bits_at_[x25]) Xor= x26 ; x27 = old_value_at_[x25]; x24,x28 = trash }", @@ -5010,7 +4948,6 @@ fn test_aarch64_binemit() { Inst::AtomicRMW { ty: I32, op: inst_common::AtomicRmwOp::Xchg, - srcloc: None, }, "BF3B03D53B7F5F88FC031AAA3C7F1888B8FFFFB5BF3B03D5", "atomically { 32_bits_at_[x25]) Xchg= x26 ; x27 = old_value_at_[x25]; x24,x28 = trash }", @@ -5019,7 +4956,6 @@ fn test_aarch64_binemit() { insns.push(( Inst::AtomicCAS { ty: I8, - srcloc: None, }, "BF3B03D53B7F5F08581F40927F0318EB610000543C7F180878FFFFB5BF3B03D5", "atomically { compare-and-swap(8_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }" @@ -5028,7 +4964,6 @@ fn test_aarch64_binemit() { insns.push(( Inst::AtomicCAS { ty: I64, - srcloc: None, }, "BF3B03D53B7F5FC8F8031AAA7F0318EB610000543C7F18C878FFFFB5BF3B03D5", "atomically { compare-and-swap(64_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }" @@ -5039,7 +4974,6 @@ fn test_aarch64_binemit() { ty: I8, r_data: writable_xreg(7), r_addr: xreg(28), - srcloc: None, }, "BF3B03D587034039", "atomically { x7 = zero_extend_8_bits_at[x28] }", @@ -5050,7 +4984,6 @@ fn test_aarch64_binemit() { ty: I64, r_data: writable_xreg(28), r_addr: xreg(7), - srcloc: None, }, "BF3B03D5FC0040F9", "atomically { x28 = zero_extend_64_bits_at[x7] }", @@ -5061,7 +4994,6 @@ fn test_aarch64_binemit() { ty: I16, r_data: xreg(17), r_addr: xreg(8), - srcloc: None, }, "11010079BF3B03D5", "atomically { 16_bits_at[x8] = x17 }", @@ -5072,7 +5004,6 @@ fn test_aarch64_binemit() { ty: I32, r_data: xreg(18), r_addr: xreg(7), - srcloc: None, }, "F20000B9BF3B03D5", "atomically { 32_bits_at[x7] = x18 }", diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index d99f1b45d0..c7112299f8 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -420,7 +420,6 @@ pub struct CallInfo { pub dest: ExternalName, pub uses: Vec, pub defs: Vec>, - pub loc: SourceLoc, pub opcode: Opcode, pub caller_callconv: CallConv, pub callee_callconv: CallConv, @@ -433,7 +432,6 @@ pub struct CallIndInfo { pub rn: Reg, pub uses: Vec, pub defs: Vec>, - pub loc: SourceLoc, pub opcode: Opcode, pub caller_callconv: CallConv, pub callee_callconv: CallConv, @@ -524,68 +522,57 @@ pub enum Inst { ULoad8 { rd: Writable, mem: AMode, - srcloc: Option, }, /// A signed (sign-extending) 8-bit load. SLoad8 { rd: Writable, mem: AMode, - srcloc: Option, }, /// An unsigned (zero-extending) 16-bit load. ULoad16 { rd: Writable, mem: AMode, - srcloc: Option, }, /// A signed (sign-extending) 16-bit load. SLoad16 { rd: Writable, mem: AMode, - srcloc: Option, }, /// An unsigned (zero-extending) 32-bit load. ULoad32 { rd: Writable, mem: AMode, - srcloc: Option, }, /// A signed (sign-extending) 32-bit load. SLoad32 { rd: Writable, mem: AMode, - srcloc: Option, }, /// A 64-bit load. ULoad64 { rd: Writable, mem: AMode, - srcloc: Option, }, /// An 8-bit store. Store8 { rd: Reg, mem: AMode, - srcloc: Option, }, /// A 16-bit store. Store16 { rd: Reg, mem: AMode, - srcloc: Option, }, /// A 32-bit store. Store32 { rd: Reg, mem: AMode, - srcloc: Option, }, /// A 64-bit store. Store64 { rd: Reg, mem: AMode, - srcloc: Option, }, /// A store of a pair of registers. @@ -686,7 +673,6 @@ pub enum Inst { AtomicRMW { ty: Type, // I8, I16, I32 or I64 op: inst_common::AtomicRmwOp, - srcloc: Option, }, /// Similar to AtomicRMW, a compare-and-swap operation implemented using a load-linked @@ -703,7 +689,6 @@ pub enum Inst { /// x24 (wr) scratch reg; value afterwards has no meaning AtomicCAS { ty: Type, // I8, I16, I32 or I64 - srcloc: Option, }, /// Read `ty` bits from address `r_addr`, zero extend the loaded value to 64 bits and put it @@ -713,7 +698,6 @@ pub enum Inst { ty: Type, // I8, I16, I32 or I64 r_data: Writable, r_addr: Reg, - srcloc: Option, }, /// Write the lowest `ty` bits of `r_data` to address `r_addr`, with a memory fence @@ -723,7 +707,6 @@ pub enum Inst { ty: Type, // I8, I16, I32 or I64 r_data: Reg, r_addr: Reg, - srcloc: Option, }, /// A memory fence. This must provide ordering to ensure that, at a minimum, neither loads @@ -798,37 +781,31 @@ pub enum Inst { FpuLoad32 { rd: Writable, mem: AMode, - srcloc: Option, }, /// Floating-point store, single-precision (32 bit). FpuStore32 { rd: Reg, mem: AMode, - srcloc: Option, }, /// Floating-point load, double-precision (64 bit). FpuLoad64 { rd: Writable, mem: AMode, - srcloc: Option, }, /// Floating-point store, double-precision (64 bit). FpuStore64 { rd: Reg, mem: AMode, - srcloc: Option, }, /// Floating-point/vector load, 128 bit. FpuLoad128 { rd: Writable, mem: AMode, - srcloc: Option, }, /// Floating-point/vector store, 128 bit. FpuStore128 { rd: Reg, mem: AMode, - srcloc: Option, }, LoadFpuConst64 { @@ -1037,7 +1014,6 @@ pub enum Inst { rd: Writable, rn: Reg, size: VectorSize, - srcloc: Option, }, /// Move to the NZCV flags (actually a `MSR NZCV, Xn` insn). @@ -1095,7 +1071,7 @@ pub enum Inst { /// of this condition in a branch that skips the trap instruction.) TrapIf { kind: CondBrKind, - trap_info: (SourceLoc, TrapCode), + trap_code: TrapCode, }, /// An indirect branch through a register, augmented with set of all @@ -1111,7 +1087,7 @@ pub enum Inst { /// An instruction guaranteed to always be undefined and to trigger an illegal instruction at /// runtime. Udf { - trap_info: (SourceLoc, TrapCode), + trap_code: TrapCode, }, /// Compute the address (using a PC-relative offset) of a memory location, using the `ADR` @@ -1146,7 +1122,6 @@ pub enum Inst { LoadExtName { rd: Writable, name: Box, - srcloc: SourceLoc, offset: i64, }, @@ -1457,47 +1432,22 @@ impl Inst { /// Generic constructor for a load (zero-extending where appropriate). pub fn gen_load(into_reg: Writable, mem: AMode, ty: Type) -> Inst { match ty { - B1 | B8 | I8 => Inst::ULoad8 { - rd: into_reg, - mem, - srcloc: None, - }, - B16 | I16 => Inst::ULoad16 { - rd: into_reg, - mem, - srcloc: None, - }, - B32 | I32 | R32 => Inst::ULoad32 { - rd: into_reg, - mem, - srcloc: None, - }, - B64 | I64 | R64 => Inst::ULoad64 { - rd: into_reg, - mem, - srcloc: None, - }, - F32 => Inst::FpuLoad32 { - rd: into_reg, - mem, - srcloc: None, - }, - F64 => Inst::FpuLoad64 { - rd: into_reg, - mem, - srcloc: None, - }, + B1 | B8 | I8 => Inst::ULoad8 { rd: into_reg, mem }, + B16 | I16 => Inst::ULoad16 { rd: into_reg, mem }, + B32 | I32 | R32 => Inst::ULoad32 { rd: into_reg, mem }, + B64 | I64 | R64 => Inst::ULoad64 { rd: into_reg, mem }, + F32 => Inst::FpuLoad32 { rd: into_reg, mem }, + F64 => Inst::FpuLoad64 { rd: into_reg, mem }, _ => { if ty.is_vector() { let bits = ty_bits(ty); let rd = into_reg; - let srcloc = None; if bits == 128 { - Inst::FpuLoad128 { rd, mem, srcloc } + Inst::FpuLoad128 { rd, mem } } else { assert_eq!(bits, 64); - Inst::FpuLoad64 { rd, mem, srcloc } + Inst::FpuLoad64 { rd, mem } } } else { unimplemented!("gen_load({})", ty); @@ -1509,47 +1459,22 @@ impl Inst { /// Generic constructor for a store. pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type) -> Inst { match ty { - B1 | B8 | I8 => Inst::Store8 { - rd: from_reg, - mem, - srcloc: None, - }, - B16 | I16 => Inst::Store16 { - rd: from_reg, - mem, - srcloc: None, - }, - B32 | I32 | R32 => Inst::Store32 { - rd: from_reg, - mem, - srcloc: None, - }, - B64 | I64 | R64 => Inst::Store64 { - rd: from_reg, - mem, - srcloc: None, - }, - F32 => Inst::FpuStore32 { - rd: from_reg, - mem, - srcloc: None, - }, - F64 => Inst::FpuStore64 { - rd: from_reg, - mem, - srcloc: None, - }, + B1 | B8 | I8 => Inst::Store8 { rd: from_reg, mem }, + B16 | I16 => Inst::Store16 { rd: from_reg, mem }, + B32 | I32 | R32 => Inst::Store32 { rd: from_reg, mem }, + B64 | I64 | R64 => Inst::Store64 { rd: from_reg, mem }, + F32 => Inst::FpuStore32 { rd: from_reg, mem }, + F64 => Inst::FpuStore64 { rd: from_reg, mem }, _ => { if ty.is_vector() { let bits = ty_bits(ty); let rd = from_reg; - let srcloc = None; if bits == 128 { - Inst::FpuStore128 { rd, mem, srcloc } + Inst::FpuStore128 { rd, mem } } else { assert_eq!(bits, 64); - Inst::FpuStore64 { rd, mem, srcloc } + Inst::FpuStore64 { rd, mem } } } else { unimplemented!("gen_store({})", ty); @@ -3024,37 +2949,30 @@ impl Inst { &Inst::ULoad8 { rd, ref mem, - srcloc: _srcloc, } | &Inst::SLoad8 { rd, ref mem, - srcloc: _srcloc, } | &Inst::ULoad16 { rd, ref mem, - srcloc: _srcloc, } | &Inst::SLoad16 { rd, ref mem, - srcloc: _srcloc, } | &Inst::ULoad32 { rd, ref mem, - srcloc: _srcloc, } | &Inst::SLoad32 { rd, ref mem, - srcloc: _srcloc, } | &Inst::ULoad64 { rd, ref mem, - srcloc: _srcloc, .. } => { let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state); @@ -3087,22 +3005,18 @@ impl Inst { &Inst::Store8 { rd, ref mem, - srcloc: _srcloc, } | &Inst::Store16 { rd, ref mem, - srcloc: _srcloc, } | &Inst::Store32 { rd, ref mem, - srcloc: _srcloc, } | &Inst::Store64 { rd, ref mem, - srcloc: _srcloc, .. } => { let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state); @@ -3841,7 +3755,6 @@ impl Inst { rd, ref name, offset, - srcloc: _srcloc, } => { let rd = rd.show_rru(mb_rru); format!("ldr {}, 8 ; b 12 ; data {:?} + {}", rd, name, offset) diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs index 957d15c57c..6c2e33504e 100644 --- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs +++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs @@ -484,9 +484,9 @@ pub(crate) fn lower_insn_to_regs>( // msub rd, rd, rm, rn ; rd = rn - rd * rm // Check for divide by 0. - let trap_info = (ctx.srcloc(insn), TrapCode::IntegerDivisionByZero); + let trap_code = TrapCode::IntegerDivisionByZero; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Zero(rm), }); @@ -507,9 +507,9 @@ pub(crate) fn lower_insn_to_regs>( // udf ; signed overflow // Check for divide by 0. - let trap_info = (ctx.srcloc(insn), TrapCode::IntegerDivisionByZero); + let trap_code = TrapCode::IntegerDivisionByZero; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Zero(rm), }); @@ -535,9 +535,9 @@ pub(crate) fn lower_insn_to_regs>( nzcv: NZCV::new(false, false, false, false), cond: Cond::Eq, }); - let trap_info = (ctx.srcloc(insn), TrapCode::IntegerOverflow); + let trap_code = TrapCode::IntegerOverflow; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Cond(Cond::Vs), }); } else { @@ -545,9 +545,9 @@ pub(crate) fn lower_insn_to_regs>( // udf ; divide by zero // Check for divide by 0. - let trap_info = (ctx.srcloc(insn), TrapCode::IntegerDivisionByZero); + let trap_code = TrapCode::IntegerDivisionByZero; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Zero(rm), }); } @@ -1161,27 +1161,20 @@ pub(crate) fn lower_insn_to_regs>( let mem = lower_address(ctx, elem_ty, &inputs[..], off); let rd = get_output_reg(ctx, outputs[0]); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; - ctx.emit(match (ty_bits(elem_ty), sign_extend, is_float) { - (1, _, _) => Inst::ULoad8 { rd, mem, srcloc }, - (8, false, _) => Inst::ULoad8 { rd, mem, srcloc }, - (8, true, _) => Inst::SLoad8 { rd, mem, srcloc }, - (16, false, _) => Inst::ULoad16 { rd, mem, srcloc }, - (16, true, _) => Inst::SLoad16 { rd, mem, srcloc }, - (32, false, false) => Inst::ULoad32 { rd, mem, srcloc }, - (32, true, false) => Inst::SLoad32 { rd, mem, srcloc }, - (32, _, true) => Inst::FpuLoad32 { rd, mem, srcloc }, - (64, _, false) => Inst::ULoad64 { rd, mem, srcloc }, + (1, _, _) => Inst::ULoad8 { rd, mem }, + (8, false, _) => Inst::ULoad8 { rd, mem }, + (8, true, _) => Inst::SLoad8 { rd, mem }, + (16, false, _) => Inst::ULoad16 { rd, mem }, + (16, true, _) => Inst::SLoad16 { rd, mem }, + (32, false, false) => Inst::ULoad32 { rd, mem }, + (32, true, false) => Inst::SLoad32 { rd, mem }, + (32, _, true) => Inst::FpuLoad32 { rd, mem }, + (64, _, false) => Inst::ULoad64 { rd, mem }, // Note that we treat some of the vector loads as scalar floating-point loads, // which is correct in a little endian environment. - (64, _, true) => Inst::FpuLoad64 { rd, mem, srcloc }, - (128, _, _) => Inst::FpuLoad128 { rd, mem, srcloc }, + (64, _, true) => Inst::FpuLoad64 { rd, mem }, + (128, _, _) => Inst::FpuLoad128 { rd, mem }, _ => panic!("Unsupported size in load"), }); @@ -1209,14 +1202,8 @@ pub(crate) fn lower_insn_to_regs>( let off = ctx.data(insn).load_store_offset().unwrap(); let ty = ty.unwrap(); let mem = lower_address(ctx, ty.lane_type(), &inputs[..], off); - let memflags = ctx.memflags(insn).expect("memory flags"); let rd = get_output_reg(ctx, outputs[0]); let size = VectorSize::from_ty(ty); - let srcloc = if memflags.notrap() { - None - } else { - Some(ctx.srcloc(insn)) - }; let tmp = ctx.alloc_tmp(RegClass::I64, I64); ctx.emit(Inst::LoadAddr { rd: tmp, mem }); @@ -1224,7 +1211,6 @@ pub(crate) fn lower_insn_to_regs>( rd, rn: tmp.to_reg(), size, - srcloc, }); } @@ -1249,21 +1235,14 @@ pub(crate) fn lower_insn_to_regs>( let mem = lower_address(ctx, elem_ty, &inputs[1..], off); let rd = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; - ctx.emit(match (ty_bits(elem_ty), is_float) { - (1, _) | (8, _) => Inst::Store8 { rd, mem, srcloc }, - (16, _) => Inst::Store16 { rd, mem, srcloc }, - (32, false) => Inst::Store32 { rd, mem, srcloc }, - (32, true) => Inst::FpuStore32 { rd, mem, srcloc }, - (64, false) => Inst::Store64 { rd, mem, srcloc }, - (64, true) => Inst::FpuStore64 { rd, mem, srcloc }, - (128, _) => Inst::FpuStore128 { rd, mem, srcloc }, + (1, _) | (8, _) => Inst::Store8 { rd, mem }, + (16, _) => Inst::Store16 { rd, mem }, + (32, false) => Inst::Store32 { rd, mem }, + (32, true) => Inst::FpuStore32 { rd, mem }, + (64, false) => Inst::Store64 { rd, mem }, + (64, true) => Inst::FpuStore64 { rd, mem }, + (128, _) => Inst::FpuStore128 { rd, mem }, _ => panic!("Unsupported size in store"), }); } @@ -1291,12 +1270,6 @@ pub(crate) fn lower_insn_to_regs>( let mut r_arg2 = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None); let ty_access = ty.unwrap(); assert!(is_valid_atomic_transaction_ty(ty_access)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; // Make sure that both args are in virtual regs, since in effect // we have to do a parallel copy to get them safely to the AtomicRMW input // regs, and that's not guaranteed safe if either is in a real reg. @@ -1307,11 +1280,7 @@ pub(crate) fn lower_insn_to_regs>( ctx.emit(Inst::gen_move(Writable::from_reg(xreg(26)), r_arg2, I64)); // Now the AtomicRMW insn itself let op = inst_common::AtomicRmwOp::from(ctx.data(insn).atomic_rmw_op().unwrap()); - ctx.emit(Inst::AtomicRMW { - ty: ty_access, - op, - srcloc, - }); + ctx.emit(Inst::AtomicRMW { ty: ty_access, op }); // And finally, copy the preordained AtomicRMW output reg to its destination. ctx.emit(Inst::gen_move(r_dst, xreg(27), I64)); // Also, x24 and x28 are trashed. `fn aarch64_get_regs` must mention that. @@ -1327,12 +1296,6 @@ pub(crate) fn lower_insn_to_regs>( let mut r_replacement = put_input_in_reg(ctx, inputs[2], NarrowValueMode::None); let ty_access = ty.unwrap(); assert!(is_valid_atomic_transaction_ty(ty_access)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; // Make sure that all three args are in virtual regs. See corresponding comment // for `Opcode::AtomicRmw` above. r_addr = ctx.ensure_in_vreg(r_addr, I64); @@ -1351,10 +1314,7 @@ pub(crate) fn lower_insn_to_regs>( I64, )); // Now the AtomicCAS itself, implemented in the normal way, with an LL-SC loop - ctx.emit(Inst::AtomicCAS { - ty: ty_access, - srcloc, - }); + ctx.emit(Inst::AtomicCAS { ty: ty_access }); // And finally, copy the preordained AtomicCAS output reg to its destination. ctx.emit(Inst::gen_move(r_dst, xreg(27), I64)); // Also, x24 and x28 are trashed. `fn aarch64_get_regs` must mention that. @@ -1365,17 +1325,10 @@ pub(crate) fn lower_insn_to_regs>( let r_addr = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None); let ty_access = ty.unwrap(); assert!(is_valid_atomic_transaction_ty(ty_access)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; ctx.emit(Inst::AtomicLoad { ty: ty_access, r_data, r_addr, - srcloc, }); } @@ -1384,17 +1337,10 @@ pub(crate) fn lower_insn_to_regs>( let r_addr = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None); let ty_access = ctx.input_ty(insn, 0); assert!(is_valid_atomic_transaction_ty(ty_access)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; ctx.emit(Inst::AtomicStore { ty: ty_access, r_data, r_addr, - srcloc, }); } @@ -1811,12 +1757,12 @@ pub(crate) fn lower_insn_to_regs>( } Opcode::Trap | Opcode::ResumableTrap => { - let trap_info = (ctx.srcloc(insn), ctx.data(insn).trap_code().unwrap()); - ctx.emit_safepoint(Inst::Udf { trap_info }); + let trap_code = ctx.data(insn).trap_code().unwrap(); + ctx.emit_safepoint(Inst::Udf { trap_code }); } Opcode::Trapif | Opcode::Trapff => { - let trap_info = (ctx.srcloc(insn), ctx.data(insn).trap_code().unwrap()); + let trap_code = ctx.data(insn).trap_code().unwrap(); let cond = if maybe_input_insn(ctx, inputs[0], Opcode::IaddIfcout).is_some() { let condcode = ctx.data(insn).cond_code().unwrap(); @@ -1847,7 +1793,7 @@ pub(crate) fn lower_insn_to_regs>( }; ctx.emit_safepoint(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Cond(cond), }); } @@ -1864,11 +1810,9 @@ pub(crate) fn lower_insn_to_regs>( let rd = get_output_reg(ctx, outputs[0]); let (extname, _) = ctx.call_target(insn).unwrap(); let extname = extname.clone(); - let loc = ctx.srcloc(insn); ctx.emit(Inst::LoadExtName { rd, name: Box::new(extname), - srcloc: loc, offset: 0, }); } @@ -1881,17 +1825,14 @@ pub(crate) fn lower_insn_to_regs>( let rd = get_output_reg(ctx, outputs[0]); let (extname, _, offset) = ctx.symbol_value(insn).unwrap(); let extname = extname.clone(); - let loc = ctx.srcloc(insn); ctx.emit(Inst::LoadExtName { rd, name: Box::new(extname), - srcloc: loc, offset, }); } Opcode::Call | Opcode::CallIndirect => { - let loc = ctx.srcloc(insn); let caller_conv = ctx.abi().call_conv(); let (mut abi, inputs) = match op { Opcode::Call => { @@ -1901,7 +1842,7 @@ pub(crate) fn lower_insn_to_regs>( assert!(inputs.len() == sig.params.len()); assert!(outputs.len() == sig.returns.len()); ( - AArch64ABICaller::from_func(sig, &extname, dist, loc, caller_conv)?, + AArch64ABICaller::from_func(sig, &extname, dist, caller_conv)?, &inputs[..], ) } @@ -1911,7 +1852,7 @@ pub(crate) fn lower_insn_to_regs>( assert!(inputs.len() - 1 == sig.params.len()); assert!(outputs.len() == sig.returns.len()); ( - AArch64ABICaller::from_ptr(sig, ptr, loc, op, caller_conv)?, + AArch64ABICaller::from_ptr(sig, ptr, op, caller_conv)?, &inputs[1..], ) } @@ -2687,9 +2628,9 @@ pub(crate) fn lower_insn_to_regs>( } else { ctx.emit(Inst::FpuCmp64 { rn, rm: rn }); } - let trap_info = (ctx.srcloc(insn), TrapCode::BadConversionToInteger); + let trap_code = TrapCode::BadConversionToInteger; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Cond(lower_fp_condcode(FloatCC::Unordered)), }); @@ -2739,9 +2680,9 @@ pub(crate) fn lower_insn_to_regs>( rn, rm: tmp.to_reg(), }); - let trap_info = (ctx.srcloc(insn), TrapCode::IntegerOverflow); + let trap_code = TrapCode::IntegerOverflow; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Cond(lower_fp_condcode(low_cond).invert()), }); @@ -2751,9 +2692,9 @@ pub(crate) fn lower_insn_to_regs>( rn, rm: tmp.to_reg(), }); - let trap_info = (ctx.srcloc(insn), TrapCode::IntegerOverflow); + let trap_code = TrapCode::IntegerOverflow; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Cond(lower_fp_condcode(FloatCC::LessThan).invert()), }); } else { @@ -2792,9 +2733,9 @@ pub(crate) fn lower_insn_to_regs>( rn, rm: tmp.to_reg(), }); - let trap_info = (ctx.srcloc(insn), TrapCode::IntegerOverflow); + let trap_code = TrapCode::IntegerOverflow; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Cond(lower_fp_condcode(low_cond).invert()), }); @@ -2804,9 +2745,9 @@ pub(crate) fn lower_insn_to_regs>( rn, rm: tmp.to_reg(), }); - let trap_info = (ctx.srcloc(insn), TrapCode::IntegerOverflow); + let trap_code = TrapCode::IntegerOverflow; ctx.emit(Inst::TrapIf { - trap_info, + trap_code, kind: CondBrKind::Cond(lower_fp_condcode(FloatCC::LessThan).invert()), }); }; diff --git a/cranelift/codegen/src/isa/arm32/abi.rs b/cranelift/codegen/src/isa/arm32/abi.rs index d13e44c6a7..edf1792e52 100644 --- a/cranelift/codegen/src/isa/arm32/abi.rs +++ b/cranelift/codegen/src/isa/arm32/abi.rs @@ -2,7 +2,6 @@ use crate::ir; use crate::ir::types::*; -use crate::ir::SourceLoc; use crate::isa; use crate::isa::arm32::inst::*; use crate::machinst::*; @@ -217,7 +216,7 @@ impl ABIMachineSpec for Arm32MachineDeps { rm: limit_reg, }); insts.push(Inst::TrapIf { - trap_info: (ir::SourceLoc::default(), ir::TrapCode::StackOverflow), + trap_info: ir::TrapCode::StackOverflow, // Here `Lo` == "less than" when interpreting the two // operands as unsigned integers. cond: Cond::Lo, @@ -366,7 +365,6 @@ impl ABIMachineSpec for Arm32MachineDeps { dest: &CallDest, uses: Vec, defs: Vec>, - loc: SourceLoc, opcode: ir::Opcode, tmp: Writable, _callee_conv: isa::CallConv, @@ -381,7 +379,6 @@ impl ABIMachineSpec for Arm32MachineDeps { dest: name.clone(), uses, defs, - loc, opcode, }), }, @@ -393,7 +390,6 @@ impl ABIMachineSpec for Arm32MachineDeps { rt: tmp, name: Box::new(name.clone()), offset: 0, - srcloc: loc, }, )); insts.push(( @@ -403,7 +399,6 @@ impl ABIMachineSpec for Arm32MachineDeps { rm: tmp.to_reg(), uses, defs, - loc, opcode, }), }, @@ -416,7 +411,6 @@ impl ABIMachineSpec for Arm32MachineDeps { rm: *reg, uses, defs, - loc, opcode, }), }, diff --git a/cranelift/codegen/src/isa/arm32/inst/emit.rs b/cranelift/codegen/src/isa/arm32/inst/emit.rs index cb5b756501..5e4a412e96 100644 --- a/cranelift/codegen/src/isa/arm32/inst/emit.rs +++ b/cranelift/codegen/src/isa/arm32/inst/emit.rs @@ -1,6 +1,7 @@ //! 32-bit ARM ISA: binary code emission. use crate::binemit::{Reloc, StackMap}; +use crate::ir::SourceLoc; use crate::isa::arm32::inst::*; use core::convert::TryFrom; @@ -229,6 +230,8 @@ pub struct EmitState { pub(crate) nominal_sp_to_fp: i64, /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`. stack_map: Option, + /// Source location of next machine code instruction to be emitted. + cur_srcloc: SourceLoc, } impl MachInstEmitState for EmitState { @@ -237,12 +240,17 @@ impl MachInstEmitState for EmitState { virtual_sp_offset: 0, nominal_sp_to_fp: abi.frame_size() as i64, stack_map: None, + cur_srcloc: SourceLoc::default(), } } fn pre_safepoint(&mut self, stack_map: StackMap) { self.stack_map = Some(stack_map); } + + fn pre_sourceloc(&mut self, srcloc: SourceLoc) { + self.cur_srcloc = srcloc; + } } impl EmitState { @@ -253,6 +261,10 @@ impl EmitState { fn clear_post_insn(&mut self) { self.stack_map = None; } + + fn cur_srcloc(&self) -> SourceLoc { + self.cur_srcloc + } } pub struct EmitInfo { @@ -456,17 +468,13 @@ impl MachInstEmit for Inst { let inst = enc_32_regs(inst, None, None, None, Some(rn)); emit_32(inst, sink); } - &Inst::Store { - rt, - ref mem, - srcloc, - bits, - } => { + &Inst::Store { rt, ref mem, bits } => { let (mem_insts, mem) = mem_finalize(mem, state); for inst in mem_insts.into_iter() { inst.emit(sink, emit_info, state); } - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { // Register the offset at which the store instruction starts. sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } @@ -496,7 +504,6 @@ impl MachInstEmit for Inst { &Inst::Load { rt, ref mem, - srcloc, bits, sign_extend, } => { @@ -504,7 +511,8 @@ impl MachInstEmit for Inst { for inst in mem_insts.into_iter() { inst.emit(sink, emit_info, state); } - if let Some(srcloc) = srcloc { + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { // Register the offset at which the load instruction starts. sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); } @@ -696,23 +704,24 @@ impl MachInstEmit for Inst { } }, &Inst::Call { ref info } => { - sink.add_reloc(info.loc, Reloc::Arm32Call, &info.dest, 0); + let srcloc = state.cur_srcloc(); + sink.add_reloc(srcloc, Reloc::Arm32Call, &info.dest, 0); emit_32(0b11110_0_0000000000_11_0_1_0_00000000000, sink); if info.opcode.is_call() { - sink.add_call_site(info.loc, info.opcode); + sink.add_call_site(srcloc, info.opcode); } } &Inst::CallInd { ref info } => { + let srcloc = state.cur_srcloc(); sink.put2(0b01000111_1_0000_000 | (machreg_to_gpr(info.rm) << 3)); if info.opcode.is_call() { - sink.add_call_site(info.loc, info.opcode); + sink.add_call_site(srcloc, info.opcode); } } &Inst::LoadExtName { rt, ref name, offset, - srcloc, } => { // maybe nop2 (0|2) bytes (pc is now 4-aligned) // ldr rt, [pc, #4] 4 bytes @@ -729,7 +738,6 @@ impl MachInstEmit for Inst { let inst = Inst::Load { rt, mem, - srcloc: Some(srcloc), bits: 32, sign_extend: false, }; @@ -740,6 +748,7 @@ impl MachInstEmit for Inst { }; inst.emit(sink, emit_info, state); + let srcloc = state.cur_srcloc(); sink.add_reloc(srcloc, Reloc::Abs4, name, offset.into()); sink.put4(0); } @@ -784,7 +793,8 @@ impl MachInstEmit for Inst { sink.put2(inst); } &Inst::Udf { trap_info } => { - let (srcloc, code) = trap_info; + let srcloc = state.cur_srcloc(); + let code = trap_info; sink.add_trap(srcloc, code); sink.put2(0b11011110_00000000); } diff --git a/cranelift/codegen/src/isa/arm32/inst/emit_tests.rs b/cranelift/codegen/src/isa/arm32/inst/emit_tests.rs index e14a58fee0..73269be999 100644 --- a/cranelift/codegen/src/isa/arm32/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/arm32/inst/emit_tests.rs @@ -1244,7 +1244,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(0), mem: AMode::reg_plus_reg(rreg(1), rreg(2), 0), - srcloc: None, bits: 32, }, "41F80200", @@ -1254,7 +1253,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(8), mem: AMode::reg_plus_reg(rreg(9), rreg(10), 3), - srcloc: None, bits: 32, }, "49F83A80", @@ -1264,7 +1262,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(0), mem: AMode::RegOffset(rreg(1), 4095), - srcloc: None, bits: 32, }, "C1F8FF0F", @@ -1274,7 +1271,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(8), mem: AMode::RegOffset(rreg(9), 0), - srcloc: None, bits: 32, }, "C9F80080", @@ -1284,7 +1280,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(7), mem: AMode::RegOffset(rreg(11), 65535), - srcloc: None, bits: 32, }, "4FF6FF7C4BF80C70", @@ -1294,7 +1289,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(10), mem: AMode::RegOffset(rreg(4), 16777215), - srcloc: None, bits: 32, }, "4FF6FF7CC0F2FF0C44F80CA0", @@ -1304,7 +1298,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(0), mem: AMode::reg_plus_reg(rreg(1), rreg(2), 0), - srcloc: None, bits: 16, }, "21F80200", @@ -1314,7 +1307,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(8), mem: AMode::reg_plus_reg(rreg(9), rreg(10), 2), - srcloc: None, bits: 16, }, "29F82A80", @@ -1324,7 +1316,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(0), mem: AMode::RegOffset(rreg(1), 3210), - srcloc: None, bits: 16, }, "A1F88A0C", @@ -1334,7 +1325,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(8), mem: AMode::RegOffset(rreg(9), 1), - srcloc: None, bits: 16, }, "A9F80180", @@ -1344,7 +1334,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(7), mem: AMode::RegOffset(rreg(11), 65535), - srcloc: None, bits: 16, }, "4FF6FF7C2BF80C70", @@ -1354,7 +1343,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(10), mem: AMode::RegOffset(rreg(4), 16777215), - srcloc: None, bits: 16, }, "4FF6FF7CC0F2FF0C24F80CA0", @@ -1364,7 +1352,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(0), mem: AMode::reg_plus_reg(rreg(1), rreg(2), 0), - srcloc: None, bits: 8, }, "01F80200", @@ -1374,7 +1361,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(8), mem: AMode::reg_plus_reg(rreg(9), rreg(10), 1), - srcloc: None, bits: 8, }, "09F81A80", @@ -1384,7 +1370,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(0), mem: AMode::RegOffset(rreg(1), 4), - srcloc: None, bits: 8, }, "81F80400", @@ -1394,7 +1379,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(8), mem: AMode::RegOffset(rreg(9), 777), - srcloc: None, bits: 8, }, "89F80983", @@ -1404,7 +1388,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(7), mem: AMode::RegOffset(rreg(11), 65535), - srcloc: None, bits: 8, }, "4FF6FF7C0BF80C70", @@ -1414,7 +1397,6 @@ fn test_arm32_emit() { Inst::Store { rt: rreg(10), mem: AMode::RegOffset(rreg(4), 16777215), - srcloc: None, bits: 8, }, "4FF6FF7CC0F2FF0C04F80CA0", @@ -1424,7 +1406,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::reg_plus_reg(rreg(1), rreg(2), 0), - srcloc: None, bits: 32, sign_extend: false, }, @@ -1435,7 +1416,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::reg_plus_reg(rreg(9), rreg(10), 1), - srcloc: None, bits: 32, sign_extend: false, }, @@ -1446,7 +1426,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::RegOffset(rreg(1), 55), - srcloc: None, bits: 32, sign_extend: false, }, @@ -1457,7 +1436,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::RegOffset(rreg(9), 1234), - srcloc: None, bits: 32, sign_extend: false, }, @@ -1468,7 +1446,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(7), mem: AMode::RegOffset(rreg(11), 9876), - srcloc: None, bits: 32, sign_extend: false, }, @@ -1479,7 +1456,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(10), mem: AMode::RegOffset(rreg(4), 252645135), - srcloc: None, bits: 32, sign_extend: false, }, @@ -1490,7 +1466,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::PCRel(-56), - srcloc: None, bits: 32, sign_extend: false, }, @@ -1501,7 +1476,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::PCRel(1024), - srcloc: None, bits: 32, sign_extend: false, }, @@ -1512,7 +1486,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::reg_plus_reg(rreg(1), rreg(2), 0), - srcloc: None, bits: 16, sign_extend: true, }, @@ -1523,7 +1496,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::reg_plus_reg(rreg(9), rreg(10), 2), - srcloc: None, bits: 16, sign_extend: false, }, @@ -1534,7 +1506,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::RegOffset(rreg(1), 55), - srcloc: None, bits: 16, sign_extend: false, }, @@ -1545,7 +1516,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::RegOffset(rreg(9), 1234), - srcloc: None, bits: 16, sign_extend: true, }, @@ -1556,7 +1526,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(7), mem: AMode::RegOffset(rreg(11), 9876), - srcloc: None, bits: 16, sign_extend: true, }, @@ -1567,7 +1536,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(10), mem: AMode::RegOffset(rreg(4), 252645135), - srcloc: None, bits: 16, sign_extend: false, }, @@ -1578,7 +1546,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::PCRel(56), - srcloc: None, bits: 16, sign_extend: false, }, @@ -1589,7 +1556,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::PCRel(-1000), - srcloc: None, bits: 16, sign_extend: true, }, @@ -1600,7 +1566,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::reg_plus_reg(rreg(1), rreg(2), 0), - srcloc: None, bits: 8, sign_extend: true, }, @@ -1611,7 +1576,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::reg_plus_reg(rreg(9), rreg(10), 3), - srcloc: None, bits: 8, sign_extend: false, }, @@ -1622,7 +1586,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::RegOffset(rreg(1), 55), - srcloc: None, bits: 8, sign_extend: false, }, @@ -1633,7 +1596,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::RegOffset(rreg(9), 1234), - srcloc: None, bits: 8, sign_extend: true, }, @@ -1644,7 +1606,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(7), mem: AMode::RegOffset(rreg(11), 9876), - srcloc: None, bits: 8, sign_extend: true, }, @@ -1655,7 +1616,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(10), mem: AMode::RegOffset(rreg(4), 252645135), - srcloc: None, bits: 8, sign_extend: false, }, @@ -1666,7 +1626,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(0), mem: AMode::PCRel(72), - srcloc: None, bits: 8, sign_extend: false, }, @@ -1677,7 +1636,6 @@ fn test_arm32_emit() { Inst::Load { rt: writable_rreg(8), mem: AMode::PCRel(-1234), - srcloc: None, bits: 8, sign_extend: true, }, @@ -1961,7 +1919,7 @@ fn test_arm32_emit() { insns.push(( Inst::TrapIf { cond: Cond::Eq, - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_info: TrapCode::Interrupt, }, "40F0018000DE", "bne 2 ; udf #0", @@ -1969,14 +1927,14 @@ fn test_arm32_emit() { insns.push(( Inst::TrapIf { cond: Cond::Hs, - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_info: TrapCode::Interrupt, }, "C0F0018000DE", "blo 2 ; udf #0", )); insns.push(( Inst::Udf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_info: TrapCode::Interrupt, }, "00DE", "udf #0", diff --git a/cranelift/codegen/src/isa/arm32/inst/mod.rs b/cranelift/codegen/src/isa/arm32/inst/mod.rs index ba34e3dfcf..fff01b7d82 100644 --- a/cranelift/codegen/src/isa/arm32/inst/mod.rs +++ b/cranelift/codegen/src/isa/arm32/inst/mod.rs @@ -4,7 +4,7 @@ use crate::binemit::CodeOffset; use crate::ir::types::{B1, B16, B32, B8, I16, I32, I8, IFLAGS}; -use crate::ir::{ExternalName, Opcode, SourceLoc, TrapCode, Type}; +use crate::ir::{ExternalName, Opcode, TrapCode, Type}; use crate::machinst::*; use crate::{settings, CodegenError, CodegenResult}; @@ -83,7 +83,6 @@ pub struct CallInfo { pub dest: ExternalName, pub uses: Vec, pub defs: Vec>, - pub loc: SourceLoc, pub opcode: Opcode, } @@ -94,7 +93,6 @@ pub struct CallIndInfo { pub rm: Reg, pub uses: Vec, pub defs: Vec>, - pub loc: SourceLoc, pub opcode: Opcode, } @@ -218,7 +216,6 @@ pub enum Inst { Store { rt: Reg, mem: AMode, - srcloc: Option, bits: u8, }, @@ -227,7 +224,6 @@ pub enum Inst { Load { rt: Writable, mem: AMode, - srcloc: Option, bits: u8, sign_extend: bool, }, @@ -276,7 +272,6 @@ pub enum Inst { LoadExtName { rt: Writable, name: Box, - srcloc: SourceLoc, offset: i32, }, @@ -308,13 +303,13 @@ pub enum Inst { /// unit to the register allocator. TrapIf { cond: Cond, - trap_info: (SourceLoc, TrapCode), + trap_info: TrapCode, }, /// An instruction guaranteed to always be undefined and to trigger an illegal instruction at /// runtime. Udf { - trap_info: (SourceLoc, TrapCode), + trap_info: TrapCode, }, /// A "breakpoint" instruction, used for e.g. traps and debug breakpoints. @@ -390,7 +385,6 @@ impl Inst { Inst::Load { rt: into_reg, mem, - srcloc: None, bits, sign_extend: false, } @@ -405,7 +399,6 @@ impl Inst { Inst::Store { rt: from_reg, mem, - srcloc: None, bits, } } @@ -1189,7 +1182,6 @@ impl Inst { rt, ref name, offset, - srcloc: _srcloc, } => { let rt = rt.show_rru(mb_rru); format!("ldr {}, [pc, #4] ; b 4 ; data {:?} + {}", rt, name, offset) diff --git a/cranelift/codegen/src/isa/arm32/lower_inst.rs b/cranelift/codegen/src/isa/arm32/lower_inst.rs index 1cff717da3..05256b2540 100644 --- a/cranelift/codegen/src/isa/arm32/lower_inst.rs +++ b/cranelift/codegen/src/isa/arm32/lower_inst.rs @@ -386,19 +386,8 @@ pub(crate) fn lower_insn_to_regs>( let base = input_to_reg(ctx, inputs[1], NarrowValueMode::None); let mem = AMode::RegOffset(base, i64::from(off)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; - ctx.emit(Inst::Store { - rt, - mem, - srcloc, - bits, - }); + ctx.emit(Inst::Store { rt, mem, bits }); } Opcode::Load | Opcode::Uload8 @@ -429,17 +418,10 @@ pub(crate) fn lower_insn_to_regs>( assert_eq!(inputs.len(), 2, "only one input for store memory operands"); let base = input_to_reg(ctx, inputs[1], NarrowValueMode::None); let mem = AMode::RegOffset(base, i64::from(off)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; ctx.emit(Inst::Load { rt: out_reg, mem, - srcloc, bits, sign_extend, }); @@ -484,7 +466,7 @@ pub(crate) fn lower_insn_to_regs>( ctx.emit(Inst::Bkpt); } Opcode::Trap => { - let trap_info = (ctx.srcloc(insn), inst_trapcode(ctx.data(insn)).unwrap()); + let trap_info = inst_trapcode(ctx.data(insn)).unwrap(); ctx.emit(Inst::Udf { trap_info }) } Opcode::Trapif => { @@ -496,7 +478,7 @@ pub(crate) fn lower_insn_to_regs>( debug_assert_eq!(ctx.data(cmp_insn).opcode(), Opcode::Ifcmp); emit_cmp(ctx, cmp_insn); - let trap_info = (ctx.srcloc(insn), inst_trapcode(ctx.data(insn)).unwrap()); + let trap_info = inst_trapcode(ctx.data(insn)).unwrap(); let condcode = inst_condcode(ctx.data(insn)).unwrap(); let cond = lower_condcode(condcode); @@ -512,7 +494,6 @@ pub(crate) fn lower_insn_to_regs>( } } Opcode::Call | Opcode::CallIndirect => { - let loc = ctx.srcloc(insn); let caller_conv = ctx.abi().call_conv(); let (mut abi, inputs) = match op { Opcode::Call => { @@ -522,7 +503,7 @@ pub(crate) fn lower_insn_to_regs>( assert_eq!(inputs.len(), sig.params.len()); assert_eq!(outputs.len(), sig.returns.len()); ( - Arm32ABICaller::from_func(sig, &extname, dist, loc, caller_conv)?, + Arm32ABICaller::from_func(sig, &extname, dist, caller_conv)?, &inputs[..], ) } @@ -532,7 +513,7 @@ pub(crate) fn lower_insn_to_regs>( assert_eq!(inputs.len() - 1, sig.params.len()); assert_eq!(outputs.len(), sig.returns.len()); ( - Arm32ABICaller::from_ptr(sig, ptr, loc, op, caller_conv)?, + Arm32ABICaller::from_ptr(sig, ptr, op, caller_conv)?, &inputs[1..], ) } diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs index 9471a943c6..425f599c2e 100644 --- a/cranelift/codegen/src/isa/x64/abi.rs +++ b/cranelift/codegen/src/isa/x64/abi.rs @@ -1,7 +1,7 @@ //! Implementation of the standard x64 ABI. use crate::ir::types::*; -use crate::ir::{self, types, SourceLoc, TrapCode, Type}; +use crate::ir::{self, types, TrapCode, Type}; use crate::isa; use crate::isa::{x64::inst::*, CallConv}; use crate::machinst::abi_impl::*; @@ -252,11 +252,11 @@ impl ABIMachineSpec for X64ABIMachineSpec { _ if ty.bytes() == 16 => ExtKind::None, _ => panic!("load_stack({})", ty), }; - Inst::load(ty, mem, into_reg, ext_kind, /* infallible */ None) + Inst::load(ty, mem, into_reg, ext_kind) } fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Self::I { - Inst::store(ty, from_reg, mem, /* infallible */ None) + Inst::store(ty, from_reg, mem) } fn gen_move(to_reg: Writable, from_reg: Reg, ty: Type) -> Self::I { @@ -274,9 +274,9 @@ impl ABIMachineSpec for X64ABIMachineSpec { let ext_mode = ExtMode::new(from_bits as u16, to_bits as u16) .expect(&format!("invalid extension: {} -> {}", from_bits, to_bits)); if is_signed { - Inst::movsx_rm_r(ext_mode, RegMem::reg(from_reg), to_reg, None) + Inst::movsx_rm_r(ext_mode, RegMem::reg(from_reg), to_reg) } else { - Inst::movzx_rm_r(ext_mode, RegMem::reg(from_reg), to_reg, None) + Inst::movzx_rm_r(ext_mode, RegMem::reg(from_reg), to_reg) } } @@ -308,7 +308,6 @@ impl ABIMachineSpec for X64ABIMachineSpec { Inst::TrapIf { // NBE == "> unsigned"; args above are reversed; this tests limit_reg > rsp. cc: CC::NBE, - srcloc: SourceLoc::default(), trap_code: TrapCode::StackOverflow, }, ] @@ -335,13 +334,13 @@ impl ABIMachineSpec for X64ABIMachineSpec { assert_eq!(ty, I64); let simm32 = offset as u32; let mem = Amode::imm_reg(simm32, base); - Inst::load(ty, mem, into_reg, ExtKind::None, None) + Inst::load(ty, mem, into_reg, ExtKind::None) } fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Self::I { let simm32 = offset as u32; let mem = Amode::imm_reg(simm32, base); - Inst::store(ty, from_reg, mem, None) + Inst::store(ty, from_reg, mem) } fn gen_sp_reg_adjust(amount: i32) -> SmallVec<[Self::I; 2]> { @@ -426,7 +425,6 @@ impl ABIMachineSpec for X64ABIMachineSpec { /* bytes = */ 8, r_reg.to_reg(), Amode::imm_reg(cur_offset, regs::rsp()), - None, )); cur_offset += 8; } @@ -461,7 +459,6 @@ impl ABIMachineSpec for X64ABIMachineSpec { insts.push(Inst::mov64_m_r( Amode::imm_reg(cur_offset, regs::rsp()), Writable::from_reg(rreg.to_reg()), - None, )); cur_offset += 8; } @@ -486,7 +483,6 @@ impl ABIMachineSpec for X64ABIMachineSpec { insts.push(Inst::mov64_m_r( Amode::imm_reg(off as u32, regs::rbp()), Writable::from_reg(regs::r14()), - None, )); } @@ -498,7 +494,6 @@ impl ABIMachineSpec for X64ABIMachineSpec { dest: &CallDest, uses: Vec, defs: Vec>, - loc: SourceLoc, opcode: ir::Opcode, tmp: Writable, _callee_conv: isa::CallConv, @@ -509,7 +504,7 @@ impl ABIMachineSpec for X64ABIMachineSpec { &CallDest::ExtName(ref name, RelocDistance::Near) => { insts.push(( InstIsSafepoint::Yes, - Inst::call_known(name.clone(), uses, defs, loc, opcode), + Inst::call_known(name.clone(), uses, defs, opcode), )); } &CallDest::ExtName(ref name, RelocDistance::Far) => { @@ -519,18 +514,17 @@ impl ABIMachineSpec for X64ABIMachineSpec { dst: tmp, name: Box::new(name.clone()), offset: 0, - srcloc: loc, }, )); insts.push(( InstIsSafepoint::Yes, - Inst::call_unknown(RegMem::reg(tmp.to_reg()), uses, defs, loc, opcode), + Inst::call_unknown(RegMem::reg(tmp.to_reg()), uses, defs, opcode), )); } &CallDest::Reg(reg) => { insts.push(( InstIsSafepoint::Yes, - Inst::call_unknown(RegMem::reg(reg), uses, defs, loc, opcode), + Inst::call_unknown(RegMem::reg(reg), uses, defs, opcode), )); } } diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs index 4dbd0981a9..6e7388c66c 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit.rs @@ -1,4 +1,4 @@ -use crate::binemit::Reloc; +use crate::binemit::{Addend, Reloc}; use crate::ir::immediates::{Ieee32, Ieee64}; use crate::ir::TrapCode; use crate::isa::x64::inst::args::*; @@ -181,6 +181,7 @@ impl LegacyPrefixes { /// indicate a 64-bit operation. fn emit_std_enc_mem( sink: &mut MachBuffer, + state: &EmitState, prefixes: LegacyPrefixes, opcodes: u32, mut num_opcodes: usize, @@ -192,6 +193,11 @@ fn emit_std_enc_mem( // 64-bit integer registers, because they are part of an address // expression. But `enc_g` can be derived from a register of any class. + let srcloc = state.cur_srcloc(); + if srcloc != SourceLoc::default() { + sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); + } + prefixes.emit(sink); match mem_e { @@ -342,6 +348,7 @@ fn emit_std_enc_enc( fn emit_std_reg_mem( sink: &mut MachBuffer, + state: &EmitState, prefixes: LegacyPrefixes, opcodes: u32, num_opcodes: usize, @@ -350,7 +357,16 @@ fn emit_std_reg_mem( rex: RexFlags, ) { let enc_g = reg_enc(reg_g); - emit_std_enc_mem(sink, prefixes, opcodes, num_opcodes, enc_g, mem_e, rex); + emit_std_enc_mem( + sink, + state, + prefixes, + opcodes, + num_opcodes, + enc_g, + mem_e, + rex, + ); } fn emit_std_reg_reg( @@ -407,6 +423,18 @@ fn one_way_jmp(sink: &mut MachBuffer, cc: CC, label: MachLabel) { sink.put4(0x0); } +/// Emits a relocation, attaching the current source location as well. +fn emit_reloc( + sink: &mut MachBuffer, + state: &EmitState, + kind: Reloc, + name: &ExternalName, + addend: Addend, +) { + let srcloc = state.cur_srcloc(); + sink.add_reloc(srcloc, kind, name, addend); +} + /// The top-level emit function. /// /// Important! Do not add improved (shortened) encoding cases to existing @@ -505,13 +533,15 @@ pub(crate) fn emit( } RegMemImm::Mem { addr } => { + let amode = addr.finalize(state); emit_std_reg_mem( sink, + state, LegacyPrefixes::None, 0x0FAF, 2, reg_g.to_reg(), - &addr.finalize(state), + &amode, rex, ); } @@ -562,13 +592,15 @@ pub(crate) fn emit( RegMemImm::Mem { addr } => { // Here we revert to the "normal" G-E ordering. + let amode = addr.finalize(state); emit_std_reg_mem( sink, + state, LegacyPrefixes::None, opcode_m, 1, reg_g.to_reg(), - &addr.finalize(state), + &amode, rex, ); } @@ -616,15 +648,19 @@ pub(crate) fn emit( *src, rex_flags, ), - RegMem::Mem { addr: src } => emit_std_reg_mem( - sink, - prefix, - opcode, - num_opcodes, - dst.to_reg(), - &src.finalize(state), - rex_flags, - ), + RegMem::Mem { addr: src } => { + let amode = src.finalize(state); + emit_std_reg_mem( + sink, + state, + prefix, + opcode, + num_opcodes, + dst.to_reg(), + &amode, + rex_flags, + ); + } } } @@ -660,7 +696,6 @@ pub(crate) fn emit( size, signed, divisor, - loc, } => { let (opcode, prefix, rex_flags) = match size { 1 => (0xF6, LegacyPrefixes::None, RexFlags::clear_w()), @@ -670,7 +705,8 @@ pub(crate) fn emit( _ => unreachable!("{}", size), }; - sink.add_trap(*loc, TrapCode::IntegerDivisionByZero); + let loc = state.cur_srcloc(); + sink.add_trap(loc, TrapCode::IntegerDivisionByZero); let subopcode = if *signed { 7 } else { 6 }; match divisor { @@ -678,15 +714,10 @@ pub(crate) fn emit( let src = int_reg_enc(*reg); emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, src, rex_flags) } - RegMem::Mem { addr: src } => emit_std_enc_mem( - sink, - prefix, - opcode, - 1, - subopcode, - &src.finalize(state), - rex_flags, - ), + RegMem::Mem { addr: src } => { + let amode = src.finalize(state); + emit_std_enc_mem(sink, state, prefix, opcode, 1, subopcode, &amode, rex_flags); + } } } @@ -704,15 +735,10 @@ pub(crate) fn emit( let src = int_reg_enc(*reg); emit_std_enc_enc(sink, prefix, 0xF7, 1, subopcode, src, rex_flags) } - RegMem::Mem { addr: src } => emit_std_enc_mem( - sink, - prefix, - 0xF7, - 1, - subopcode, - &src.finalize(state), - rex_flags, - ), + RegMem::Mem { addr: src } => { + let amode = src.finalize(state); + emit_std_enc_mem(sink, state, prefix, 0xF7, 1, subopcode, &amode, rex_flags); + } } } @@ -737,7 +763,6 @@ pub(crate) fn emit( kind, size, divisor, - loc, tmp, } => { // Generates the following code sequence: @@ -773,7 +798,7 @@ pub(crate) fn emit( let inst = Inst::cmp_rmi_r(*size, RegMemImm::imm(0), divisor.to_reg()); inst.emit(sink, info, state); - let inst = Inst::trap_if(CC::Z, TrapCode::IntegerDivisionByZero, *loc); + let inst = Inst::trap_if(CC::Z, TrapCode::IntegerDivisionByZero); inst.emit(sink, info, state); let (do_op, done_label) = if kind.is_signed() { @@ -818,7 +843,7 @@ pub(crate) fn emit( } // If not equal, jump over the trap. - let inst = Inst::trap_if(CC::Z, TrapCode::IntegerOverflow, *loc); + let inst = Inst::trap_if(CC::Z, TrapCode::IntegerOverflow); inst.emit(sink, info, state); (Some(do_op), None) @@ -847,7 +872,7 @@ pub(crate) fn emit( inst.emit(sink, info, state); } - let inst = Inst::div(*size, kind.is_signed(), RegMem::reg(divisor.to_reg()), *loc); + let inst = Inst::div(*size, kind.is_signed(), RegMem::reg(divisor.to_reg())); inst.emit(sink, info, state); // Lowering takes care of moving the result back into the right register, see comment @@ -900,12 +925,7 @@ pub(crate) fn emit( emit_std_reg_reg(sink, LegacyPrefixes::None, 0x89, 1, *src, dst.to_reg(), rex); } - Inst::MovzxRmR { - ext_mode, - src, - dst, - srcloc, - } => { + Inst::MovzxRmR { ext_mode, src, dst } => { let (opcodes, num_opcodes, mut rex_flags) = match ext_mode { ExtMode::BL => { // MOVZBL is (REX.W==0) 0F B6 /r @@ -963,13 +983,9 @@ pub(crate) fn emit( RegMem::Mem { addr: src } => { let src = &src.finalize(state); - if let Some(srcloc) = *srcloc { - // Register the offset at which the actual load instruction starts. - sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); - } - emit_std_reg_mem( sink, + state, LegacyPrefixes::None, opcodes, num_opcodes, @@ -981,16 +997,12 @@ pub(crate) fn emit( } } - Inst::Mov64MR { src, dst, srcloc } => { + Inst::Mov64MR { src, dst } => { let src = &src.finalize(state); - if let Some(srcloc) = *srcloc { - // Register the offset at which the actual load instruction starts. - sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); - } - emit_std_reg_mem( sink, + state, LegacyPrefixes::None, 0x8B, 1, @@ -1000,22 +1012,22 @@ pub(crate) fn emit( ) } - Inst::LoadEffectiveAddress { addr, dst } => emit_std_reg_mem( - sink, - LegacyPrefixes::None, - 0x8D, - 1, - dst.to_reg(), - &addr.finalize(state), - RexFlags::set_w(), - ), + Inst::LoadEffectiveAddress { addr, dst } => { + let amode = addr.finalize(state); - Inst::MovsxRmR { - ext_mode, - src, - dst, - srcloc, - } => { + emit_std_reg_mem( + sink, + state, + LegacyPrefixes::None, + 0x8D, + 1, + dst.to_reg(), + &amode, + RexFlags::set_w(), + ); + } + + Inst::MovsxRmR { ext_mode, src, dst } => { let (opcodes, num_opcodes, mut rex_flags) = match ext_mode { ExtMode::BL => { // MOVSBL is (REX.W==0) 0F BE /r @@ -1065,13 +1077,9 @@ pub(crate) fn emit( RegMem::Mem { addr: src } => { let src = &src.finalize(state); - if let Some(srcloc) = *srcloc { - // Register the offset at which the actual load instruction starts. - sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); - } - emit_std_reg_mem( sink, + state, LegacyPrefixes::None, opcodes, num_opcodes, @@ -1083,19 +1091,9 @@ pub(crate) fn emit( } } - Inst::MovRM { - size, - src, - dst, - srcloc, - } => { + Inst::MovRM { size, src, dst } => { let dst = &dst.finalize(state); - if let Some(srcloc) = *srcloc { - // Register the offset at which the actual load instruction starts. - sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); - } - match size { 1 => { // This is one of the few places where the presence of a @@ -1109,13 +1107,14 @@ pub(crate) fn emit( }; // MOV r8, r/m8 is (REX.W==0) 88 /r - emit_std_reg_mem(sink, LegacyPrefixes::None, 0x88, 1, *src, dst, rex) + emit_std_reg_mem(sink, state, LegacyPrefixes::None, 0x88, 1, *src, dst, rex) } 2 => { // MOV r16, r/m16 is 66 (REX.W==0) 89 /r emit_std_reg_mem( sink, + state, LegacyPrefixes::_66, 0x89, 1, @@ -1129,6 +1128,7 @@ pub(crate) fn emit( // MOV r32, r/m32 is (REX.W==0) 89 /r emit_std_reg_mem( sink, + state, LegacyPrefixes::None, 0x89, 1, @@ -1142,6 +1142,7 @@ pub(crate) fn emit( // MOV r64, r/m64 is (REX.W==1) 89 /r emit_std_reg_mem( sink, + state, LegacyPrefixes::None, 0x89, 1, @@ -1248,7 +1249,16 @@ pub(crate) fn emit( } RegMemImm::Mem { addr } => { let addr = &addr.finalize(state); - emit_std_reg_mem(sink, prefix, opcode_bytes, 2, dst.to_reg(), addr, rex); + emit_std_reg_mem( + sink, + state, + prefix, + opcode_bytes, + 2, + dst.to_reg(), + addr, + rex, + ); } RegMemImm::Imm { .. } => unreachable!(), } @@ -1300,7 +1310,7 @@ pub(crate) fn emit( let addr = &addr.finalize(state); // Whereas here we revert to the "normal" G-E ordering. let opcode = if *size == 1 { 0x3A } else { 0x3B }; - emit_std_reg_mem(sink, prefix, opcode, 1, *reg_g, addr, rex); + emit_std_reg_mem(sink, state, prefix, opcode, 1, *reg_g, addr, rex); } RegMemImm::Imm { simm32 } => { @@ -1358,7 +1368,16 @@ pub(crate) fn emit( } RegMem::Mem { addr } => { let addr = &addr.finalize(state); - emit_std_reg_mem(sink, prefix, opcode, 2, reg_g.to_reg(), addr, rex_flags); + emit_std_reg_mem( + sink, + state, + prefix, + opcode, + 2, + reg_g.to_reg(), + addr, + rex_flags, + ); } } } @@ -1402,6 +1421,7 @@ pub(crate) fn emit( let addr = &addr.finalize(state); emit_std_enc_mem( sink, + state, LegacyPrefixes::None, 0xFF, 1, @@ -1432,25 +1452,22 @@ pub(crate) fn emit( sink.put1(0x58 + (enc_dst & 7)); } - Inst::CallKnown { - dest, loc, opcode, .. - } => { + Inst::CallKnown { dest, opcode, .. } => { if let Some(s) = state.take_stack_map() { sink.add_stack_map(StackMapExtent::UpcomingBytes(5), s); } sink.put1(0xE8); // The addend adjusts for the difference between the end of the instruction and the // beginning of the immediate field. - sink.add_reloc(*loc, Reloc::X86CallPCRel4, &dest, -4); + emit_reloc(sink, state, Reloc::X86CallPCRel4, &dest, -4); sink.put4(0); if opcode.is_call() { - sink.add_call_site(*loc, *opcode); + let loc = state.cur_srcloc(); + sink.add_call_site(loc, *opcode); } } - Inst::CallUnknown { - dest, opcode, loc, .. - } => { + Inst::CallUnknown { dest, opcode, .. } => { let start_offset = sink.cur_offset(); match dest { RegMem::Reg { reg } => { @@ -1470,6 +1487,7 @@ pub(crate) fn emit( let addr = &addr.finalize(state); emit_std_enc_mem( sink, + state, LegacyPrefixes::None, 0xFF, 1, @@ -1483,7 +1501,8 @@ pub(crate) fn emit( sink.add_stack_map(StackMapExtent::StartedAtOffset(start_offset), s); } if opcode.is_call() { - sink.add_call_site(*loc, *opcode); + let loc = state.cur_srcloc(); + sink.add_call_site(loc, *opcode); } } @@ -1566,6 +1585,7 @@ pub(crate) fn emit( let addr = &addr.finalize(state); emit_std_enc_mem( sink, + state, LegacyPrefixes::None, 0xFF, 1, @@ -1609,7 +1629,7 @@ pub(crate) fn emit( one_way_jmp(sink, CC::NB, *default_target); // idx unsigned >= jmp table size // Copy the index (and make sure to clear the high 32-bits lane of tmp2). - let inst = Inst::movzx_rm_r(ExtMode::LQ, RegMem::reg(*idx), *tmp2, None); + let inst = Inst::movzx_rm_r(ExtMode::LQ, RegMem::reg(*idx), *tmp2); inst.emit(sink, info, state); // Load base address of jump table. @@ -1623,7 +1643,6 @@ pub(crate) fn emit( ExtMode::LQ, RegMem::mem(Amode::imm_reg_reg_shift(0, tmp1.to_reg(), tmp2.to_reg(), 2)), *tmp2, - None, ); inst.emit(sink, info, state); @@ -1655,18 +1674,14 @@ pub(crate) fn emit( } } - Inst::TrapIf { - cc, - trap_code, - srcloc, - } => { + Inst::TrapIf { cc, trap_code } => { let else_label = sink.get_label(); // Jump over if the invert of CC is set (i.e. CC is not set). one_way_jmp(sink, cc.invert(), else_label); // Trap! - let inst = Inst::trap(*srcloc, *trap_code); + let inst = Inst::trap(*trap_code); inst.emit(sink, info, state); sink.bind_label(else_label); @@ -1676,7 +1691,6 @@ pub(crate) fn emit( op, src: src_e, dst: reg_g, - srcloc, } => { let rex = RexFlags::clear_w(); @@ -1715,11 +1729,16 @@ pub(crate) fn emit( } RegMem::Mem { addr } => { let addr = &addr.finalize(state); - if let Some(srcloc) = *srcloc { - // Register the offset at which the actual load instruction starts. - sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); - } - emit_std_reg_mem(sink, prefix, opcode, num_opcodes, reg_g.to_reg(), addr, rex); + emit_std_reg_mem( + sink, + state, + prefix, + opcode, + num_opcodes, + reg_g.to_reg(), + addr, + rex, + ); } }; } @@ -1728,7 +1747,6 @@ pub(crate) fn emit( op, src: src_e, dst: reg_g, - srcloc, } => { let rex = RexFlags::clear_w(); let (prefix, opcode, length) = match op { @@ -1823,12 +1841,17 @@ pub(crate) fn emit( emit_std_reg_reg(sink, prefix, opcode, length, reg_g.to_reg(), *reg_e, rex); } RegMem::Mem { addr } => { - if let Some(srcloc) = *srcloc { - // Register the offset at which the actual load instruction starts. - sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); - } let addr = &addr.finalize(state); - emit_std_reg_mem(sink, prefix, opcode, length, reg_g.to_reg(), addr, rex); + emit_std_reg_mem( + sink, + state, + prefix, + opcode, + length, + reg_g.to_reg(), + addr, + rex, + ); } } } @@ -1897,7 +1920,7 @@ pub(crate) fn emit( // and negative zero. These instructions merge the sign bits in that // case, and are no-ops otherwise. let op = if *is_min { or_op } else { and_op }; - let inst = Inst::xmm_rm_r(op, RegMem::reg(*lhs), *rhs_dst, None); + let inst = Inst::xmm_rm_r(op, RegMem::reg(*lhs), *rhs_dst); inst.emit(sink, info, state); let inst = Inst::jmp_known(done); @@ -1907,13 +1930,13 @@ pub(crate) fn emit( // read-only operand: perform an addition between the two operands, which has the // desired NaN propagation effects. sink.bind_label(propagate_nan); - let inst = Inst::xmm_rm_r(add_op, RegMem::reg(*lhs), *rhs_dst, None); + let inst = Inst::xmm_rm_r(add_op, RegMem::reg(*lhs), *rhs_dst); inst.emit(sink, info, state); one_way_jmp(sink, CC::P, done); sink.bind_label(do_min_max); - let inst = Inst::xmm_rm_r(min_max_op, RegMem::reg(*lhs), *rhs_dst, None); + let inst = Inst::xmm_rm_r(min_max_op, RegMem::reg(*lhs), *rhs_dst); inst.emit(sink, info, state); sink.bind_label(done); @@ -1925,7 +1948,6 @@ pub(crate) fn emit( dst, imm, is64, - srcloc, } => { let (prefix, opcode, len) = match op { SseOpcode::Cmpps => (LegacyPrefixes::None, 0x0FC2, 2), @@ -1964,16 +1986,12 @@ pub(crate) fn emit( } } RegMem::Mem { addr } => { - if let Some(srcloc) = *srcloc { - // Register the offset at which the actual load instruction starts. - sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); - } let addr = &addr.finalize(state); assert!( !regs_swapped, "No existing way to encode a mem argument in the ModRM r/m field." ); - emit_std_reg_mem(sink, prefix, opcode, len, dst.to_reg(), addr, rex); + emit_std_reg_mem(sink, state, prefix, opcode, len, dst.to_reg(), addr, rex); } } sink.put1(*imm); @@ -1981,7 +1999,7 @@ pub(crate) fn emit( Inst::XmmLoadConst { src, dst, ty } => { let load_offset = Amode::rip_relative(sink.get_label_for_constant(*src)); - let load = Inst::load(*ty, load_offset, *dst, ExtKind::None, None); + let load = Inst::load(*ty, load_offset, *dst, ExtKind::None); load.emit(sink, info, state); } @@ -1990,12 +2008,7 @@ pub(crate) fn emit( // emitted. } - Inst::XmmMovRM { - op, - src, - dst, - srcloc, - } => { + Inst::XmmMovRM { op, src, dst } => { let (prefix, opcode) = match op { SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F29), SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F29), @@ -2008,11 +2021,16 @@ pub(crate) fn emit( _ => unimplemented!("Opcode {:?} not implemented", op), }; let dst = &dst.finalize(state); - if let Some(srcloc) = *srcloc { - // Register the offset at which the actual load instruction starts. - sink.add_trap(srcloc, TrapCode::HeapOutOfBounds); - } - emit_std_reg_mem(sink, prefix, opcode, 2, *src, dst, RexFlags::clear_w()); + emit_std_reg_mem( + sink, + state, + prefix, + opcode, + 2, + *src, + dst, + RexFlags::clear_w(), + ); } Inst::XmmToGpr { @@ -2070,7 +2088,7 @@ pub(crate) fn emit( } RegMem::Mem { addr } => { let addr = &addr.finalize(state); - emit_std_reg_mem(sink, prefix, opcode, 2, reg_g.to_reg(), addr, rex); + emit_std_reg_mem(sink, state, prefix, opcode, 2, reg_g.to_reg(), addr, rex); } } } @@ -2090,7 +2108,7 @@ pub(crate) fn emit( } RegMem::Mem { addr } => { let addr = &addr.finalize(state); - emit_std_reg_mem(sink, prefix, opcode, len, *dst, addr, rex); + emit_std_reg_mem(sink, state, prefix, opcode, len, *dst, addr, rex); } } } @@ -2185,7 +2203,7 @@ pub(crate) fn emit( } else { SseOpcode::Addss }; - let inst = Inst::xmm_rm_r(add_op, RegMem::reg(dst.to_reg()), *dst, None); + let inst = Inst::xmm_rm_r(add_op, RegMem::reg(dst.to_reg()), *dst); inst.emit(sink, info, state); sink.bind_label(done); @@ -2199,7 +2217,6 @@ pub(crate) fn emit( dst, tmp_gpr, tmp_xmm, - srcloc, } => { // Emits the following common sequence: // @@ -2292,12 +2309,8 @@ pub(crate) fn emit( // If the input was positive, saturate to INT_MAX. // Zero out tmp_xmm. - let inst = Inst::xmm_rm_r( - SseOpcode::Xorpd, - RegMem::reg(tmp_xmm.to_reg()), - *tmp_xmm, - None, - ); + let inst = + Inst::xmm_rm_r(SseOpcode::Xorpd, RegMem::reg(tmp_xmm.to_reg()), *tmp_xmm); inst.emit(sink, info, state); let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm.to_reg()); @@ -2317,7 +2330,7 @@ pub(crate) fn emit( } else { let check_positive = sink.get_label(); - let inst = Inst::trap(*srcloc, TrapCode::BadConversionToInteger); + let inst = Inst::trap(TrapCode::BadConversionToInteger); inst.emit(sink, info, state); // Check if INT_MIN was the correct result: determine the smallest floating point @@ -2360,7 +2373,7 @@ pub(crate) fn emit( // jump over trap if src >= or > threshold one_way_jmp(sink, no_overflow_cc, check_positive); - let inst = Inst::trap(*srcloc, TrapCode::IntegerOverflow); + let inst = Inst::trap(TrapCode::IntegerOverflow); inst.emit(sink, info, state); // If positive, it was a real overflow. @@ -2368,12 +2381,8 @@ pub(crate) fn emit( sink.bind_label(check_positive); // Zero out the tmp_xmm register. - let inst = Inst::xmm_rm_r( - SseOpcode::Xorpd, - RegMem::reg(tmp_xmm.to_reg()), - *tmp_xmm, - None, - ); + let inst = + Inst::xmm_rm_r(SseOpcode::Xorpd, RegMem::reg(tmp_xmm.to_reg()), *tmp_xmm); inst.emit(sink, info, state); let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm.to_reg()); @@ -2381,7 +2390,7 @@ pub(crate) fn emit( one_way_jmp(sink, CC::NB, done); // jump over trap if 0 >= src - let inst = Inst::trap(*srcloc, TrapCode::IntegerOverflow); + let inst = Inst::trap(TrapCode::IntegerOverflow); inst.emit(sink, info, state); } @@ -2396,7 +2405,6 @@ pub(crate) fn emit( dst, tmp_gpr, tmp_xmm, - srcloc, } => { // The only difference in behavior between saturating and non-saturating is how we // handle errors. Emits the following sequence: @@ -2487,7 +2495,7 @@ pub(crate) fn emit( inst.emit(sink, info, state); } else { // Trap. - let inst = Inst::trap(*srcloc, TrapCode::BadConversionToInteger); + let inst = Inst::trap(TrapCode::BadConversionToInteger); inst.emit(sink, info, state); } @@ -2519,7 +2527,7 @@ pub(crate) fn emit( inst.emit(sink, info, state); } else { // Trap. - let inst = Inst::trap(*srcloc, TrapCode::IntegerOverflow); + let inst = Inst::trap(TrapCode::IntegerOverflow); inst.emit(sink, info, state); } @@ -2527,7 +2535,7 @@ pub(crate) fn emit( sink.bind_label(handle_large); - let inst = Inst::xmm_rm_r(sub_op, RegMem::reg(tmp_xmm.to_reg()), *src, None); + let inst = Inst::xmm_rm_r(sub_op, RegMem::reg(tmp_xmm.to_reg()), *src); inst.emit(sink, info, state); let inst = Inst::xmm_to_gpr(trunc_op, src.to_reg(), *dst, *dst_size); @@ -2556,7 +2564,7 @@ pub(crate) fn emit( let inst = Inst::jmp_known(done); inst.emit(sink, info, state); } else { - let inst = Inst::trap(*srcloc, TrapCode::IntegerOverflow); + let inst = Inst::trap(TrapCode::IntegerOverflow); inst.emit(sink, info, state); } @@ -2582,18 +2590,13 @@ pub(crate) fn emit( sink.bind_label(done); } - Inst::LoadExtName { - dst, - name, - offset, - srcloc, - } => { + Inst::LoadExtName { dst, name, offset } => { // The full address can be encoded in the register, with a relocation. // Generates: movabsq $name, %dst let enc_dst = int_reg_enc(dst.to_reg()); sink.put1(0x48 | ((enc_dst >> 3) & 1)); sink.put1(0xB8 | (enc_dst & 7)); - sink.add_reloc(*srcloc, Reloc::Abs8, name, *offset); + emit_reloc(sink, state, Reloc::Abs8, name, *offset); if info.flags().emit_all_ones_funcaddrs() { sink.put8(u64::max_value()); } else { @@ -2601,15 +2604,7 @@ pub(crate) fn emit( } } - Inst::LockCmpxchg { - ty, - src, - dst, - srcloc, - } => { - if let Some(srcloc) = srcloc { - sink.add_trap(*srcloc, TrapCode::HeapOutOfBounds); - } + Inst::LockCmpxchg { ty, src, dst } => { // lock cmpxchg{b,w,l,q} %src, (dst) // Note that 0xF0 is the Lock prefix. let (prefix, rex, opcodes) = match *ty { @@ -2626,10 +2621,11 @@ pub(crate) fn emit( types::I64 => (LegacyPrefixes::_F0, RexFlags::set_w(), 0x0FB1), _ => unreachable!(), }; - emit_std_reg_mem(sink, prefix, opcodes, 2, *src, &dst.finalize(state), rex); + let amode = dst.finalize(state); + emit_std_reg_mem(sink, state, prefix, opcodes, 2, *src, &amode, rex); } - Inst::AtomicRmwSeq { ty, op, srcloc } => { + Inst::AtomicRmwSeq { ty, op } => { // Emit this: // // mov{zbq,zwq,zlq,q} (%r9), %rax // rax = old value @@ -2657,7 +2653,7 @@ pub(crate) fn emit( // mov{zbq,zwq,zlq,q} (%r9), %rax // No need to call `add_trap` here, since the `i1` emit will do that. - let i1 = Inst::load(*ty, amode.clone(), rax_w, ExtKind::ZeroExtend, *srcloc); + let i1 = Inst::load(*ty, amode.clone(), rax_w, ExtKind::ZeroExtend); i1.emit(sink, info, state); // again: @@ -2690,7 +2686,6 @@ pub(crate) fn emit( ty: *ty, src: r11, dst: amode.into(), - srcloc: *srcloc, }; i4.emit(sink, info, state); @@ -2712,8 +2707,9 @@ pub(crate) fn emit( sink.put1(0xcc); } - Inst::Ud2 { trap_info } => { - sink.add_trap(trap_info.0, trap_info.1); + Inst::Ud2 { trap_code } => { + let cur_srcloc = state.cur_srcloc(); + sink.add_trap(cur_srcloc, *trap_code); if let Some(s) = state.take_stack_map() { sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s); } diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs index 0e6ad1d118..06092d498a 100644 --- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs @@ -98,82 +98,82 @@ fn test_x64_emit() { // // Addr_IR, offset zero insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, rax), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, rax), w_rdi), "488B38", "movq 0(%rax), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, rbx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, rbx), w_rdi), "488B3B", "movq 0(%rbx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, rcx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, rcx), w_rdi), "488B39", "movq 0(%rcx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, rdx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, rdx), w_rdi), "488B3A", "movq 0(%rdx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, rbp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, rbp), w_rdi), "488B7D00", "movq 0(%rbp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, rsp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, rsp), w_rdi), "488B3C24", "movq 0(%rsp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, rsi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, rsi), w_rdi), "488B3E", "movq 0(%rsi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, rdi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, rdi), w_rdi), "488B3F", "movq 0(%rdi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, r8), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, r8), w_rdi), "498B38", "movq 0(%r8), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, r9), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, r9), w_rdi), "498B39", "movq 0(%r9), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, r10), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, r10), w_rdi), "498B3A", "movq 0(%r10), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, r11), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, r11), w_rdi), "498B3B", "movq 0(%r11), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, r12), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, r12), w_rdi), "498B3C24", "movq 0(%r12), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, r13), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, r13), w_rdi), "498B7D00", "movq 0(%r13), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, r14), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, r14), w_rdi), "498B3E", "movq 0(%r14), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0, r15), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0, r15), w_rdi), "498B3F", "movq 0(%r15), %rdi", )); @@ -181,82 +181,82 @@ fn test_x64_emit() { // ======================================================== // Addr_IR, offset max simm8 insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, rax), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, rax), w_rdi), "488B787F", "movq 127(%rax), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, rbx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, rbx), w_rdi), "488B7B7F", "movq 127(%rbx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, rcx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, rcx), w_rdi), "488B797F", "movq 127(%rcx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, rdx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, rdx), w_rdi), "488B7A7F", "movq 127(%rdx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, rbp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, rbp), w_rdi), "488B7D7F", "movq 127(%rbp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, rsp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, rsp), w_rdi), "488B7C247F", "movq 127(%rsp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, rsi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, rsi), w_rdi), "488B7E7F", "movq 127(%rsi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, rdi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, rdi), w_rdi), "488B7F7F", "movq 127(%rdi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, r8), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, r8), w_rdi), "498B787F", "movq 127(%r8), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, r9), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, r9), w_rdi), "498B797F", "movq 127(%r9), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, r10), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, r10), w_rdi), "498B7A7F", "movq 127(%r10), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, r11), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, r11), w_rdi), "498B7B7F", "movq 127(%r11), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, r12), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, r12), w_rdi), "498B7C247F", "movq 127(%r12), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, r13), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, r13), w_rdi), "498B7D7F", "movq 127(%r13), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, r14), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, r14), w_rdi), "498B7E7F", "movq 127(%r14), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(127, r15), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(127, r15), w_rdi), "498B7F7F", "movq 127(%r15), %rdi", )); @@ -264,82 +264,82 @@ fn test_x64_emit() { // ======================================================== // Addr_IR, offset min simm8 insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rax), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rax), w_rdi), "488B7880", "movq -128(%rax), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rbx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rbx), w_rdi), "488B7B80", "movq -128(%rbx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rcx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rcx), w_rdi), "488B7980", "movq -128(%rcx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rdx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rdx), w_rdi), "488B7A80", "movq -128(%rdx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rbp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rbp), w_rdi), "488B7D80", "movq -128(%rbp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rsp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rsp), w_rdi), "488B7C2480", "movq -128(%rsp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rsi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rsi), w_rdi), "488B7E80", "movq -128(%rsi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rdi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rdi), w_rdi), "488B7F80", "movq -128(%rdi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r8), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r8), w_rdi), "498B7880", "movq -128(%r8), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r9), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r9), w_rdi), "498B7980", "movq -128(%r9), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r10), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r10), w_rdi), "498B7A80", "movq -128(%r10), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r11), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r11), w_rdi), "498B7B80", "movq -128(%r11), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r12), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r12), w_rdi), "498B7C2480", "movq -128(%r12), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r13), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r13), w_rdi), "498B7D80", "movq -128(%r13), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r14), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r14), w_rdi), "498B7E80", "movq -128(%r14), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r15), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r15), w_rdi), "498B7F80", "movq -128(%r15), %rdi", )); @@ -347,82 +347,82 @@ fn test_x64_emit() { // ======================================================== // Addr_IR, offset smallest positive simm32 insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, rax), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, rax), w_rdi), "488BB880000000", "movq 128(%rax), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, rbx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, rbx), w_rdi), "488BBB80000000", "movq 128(%rbx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, rcx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, rcx), w_rdi), "488BB980000000", "movq 128(%rcx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, rdx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, rdx), w_rdi), "488BBA80000000", "movq 128(%rdx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, rbp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, rbp), w_rdi), "488BBD80000000", "movq 128(%rbp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, rsp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, rsp), w_rdi), "488BBC2480000000", "movq 128(%rsp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, rsi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, rsi), w_rdi), "488BBE80000000", "movq 128(%rsi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, rdi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, rdi), w_rdi), "488BBF80000000", "movq 128(%rdi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, r8), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, r8), w_rdi), "498BB880000000", "movq 128(%r8), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, r9), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, r9), w_rdi), "498BB980000000", "movq 128(%r9), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, r10), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, r10), w_rdi), "498BBA80000000", "movq 128(%r10), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, r11), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, r11), w_rdi), "498BBB80000000", "movq 128(%r11), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, r12), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, r12), w_rdi), "498BBC2480000000", "movq 128(%r12), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, r13), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, r13), w_rdi), "498BBD80000000", "movq 128(%r13), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, r14), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, r14), w_rdi), "498BBE80000000", "movq 128(%r14), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(128, r15), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(128, r15), w_rdi), "498BBF80000000", "movq 128(%r15), %rdi", )); @@ -430,82 +430,82 @@ fn test_x64_emit() { // ======================================================== // Addr_IR, offset smallest negative simm32 insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rax), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rax), w_rdi), "488BB87FFFFFFF", "movq -129(%rax), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rbx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rbx), w_rdi), "488BBB7FFFFFFF", "movq -129(%rbx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rcx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rcx), w_rdi), "488BB97FFFFFFF", "movq -129(%rcx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rdx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rdx), w_rdi), "488BBA7FFFFFFF", "movq -129(%rdx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rbp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rbp), w_rdi), "488BBD7FFFFFFF", "movq -129(%rbp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rsp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rsp), w_rdi), "488BBC247FFFFFFF", "movq -129(%rsp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rsi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rsi), w_rdi), "488BBE7FFFFFFF", "movq -129(%rsi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rdi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rdi), w_rdi), "488BBF7FFFFFFF", "movq -129(%rdi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r8), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r8), w_rdi), "498BB87FFFFFFF", "movq -129(%r8), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r9), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r9), w_rdi), "498BB97FFFFFFF", "movq -129(%r9), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r10), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r10), w_rdi), "498BBA7FFFFFFF", "movq -129(%r10), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r11), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r11), w_rdi), "498BBB7FFFFFFF", "movq -129(%r11), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r12), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r12), w_rdi), "498BBC247FFFFFFF", "movq -129(%r12), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r13), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r13), w_rdi), "498BBD7FFFFFFF", "movq -129(%r13), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r14), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r14), w_rdi), "498BBE7FFFFFFF", "movq -129(%r14), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r15), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r15), w_rdi), "498BBF7FFFFFFF", "movq -129(%r15), %rdi", )); @@ -513,82 +513,82 @@ fn test_x64_emit() { // ======================================================== // Addr_IR, offset large positive simm32 insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, rax), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, rax), w_rdi), "488BB877207317", "movq 393420919(%rax), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, rbx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, rbx), w_rdi), "488BBB77207317", "movq 393420919(%rbx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, rcx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, rcx), w_rdi), "488BB977207317", "movq 393420919(%rcx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, rdx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, rdx), w_rdi), "488BBA77207317", "movq 393420919(%rdx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, rbp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, rbp), w_rdi), "488BBD77207317", "movq 393420919(%rbp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, rsp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, rsp), w_rdi), "488BBC2477207317", "movq 393420919(%rsp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, rsi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, rsi), w_rdi), "488BBE77207317", "movq 393420919(%rsi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, rdi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, rdi), w_rdi), "488BBF77207317", "movq 393420919(%rdi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, r8), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, r8), w_rdi), "498BB877207317", "movq 393420919(%r8), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, r9), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, r9), w_rdi), "498BB977207317", "movq 393420919(%r9), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, r10), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, r10), w_rdi), "498BBA77207317", "movq 393420919(%r10), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, r11), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, r11), w_rdi), "498BBB77207317", "movq 393420919(%r11), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, r12), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, r12), w_rdi), "498BBC2477207317", "movq 393420919(%r12), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, r13), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, r13), w_rdi), "498BBD77207317", "movq 393420919(%r13), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, r14), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, r14), w_rdi), "498BBE77207317", "movq 393420919(%r14), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(0x17732077, r15), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(0x17732077, r15), w_rdi), "498BBF77207317", "movq 393420919(%r15), %rdi", )); @@ -596,82 +596,82 @@ fn test_x64_emit() { // ======================================================== // Addr_IR, offset large negative simm32 insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rax), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rax), w_rdi), "488BB8D9A6BECE", "movq -826366247(%rax), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rbx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rbx), w_rdi), "488BBBD9A6BECE", "movq -826366247(%rbx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rcx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rcx), w_rdi), "488BB9D9A6BECE", "movq -826366247(%rcx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rdx), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rdx), w_rdi), "488BBAD9A6BECE", "movq -826366247(%rdx), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rbp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rbp), w_rdi), "488BBDD9A6BECE", "movq -826366247(%rbp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rsp), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rsp), w_rdi), "488BBC24D9A6BECE", "movq -826366247(%rsp), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rsi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rsi), w_rdi), "488BBED9A6BECE", "movq -826366247(%rsi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rdi), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rdi), w_rdi), "488BBFD9A6BECE", "movq -826366247(%rdi), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r8), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r8), w_rdi), "498BB8D9A6BECE", "movq -826366247(%r8), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r9), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r9), w_rdi), "498BB9D9A6BECE", "movq -826366247(%r9), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r10), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r10), w_rdi), "498BBAD9A6BECE", "movq -826366247(%r10), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r11), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r11), w_rdi), "498BBBD9A6BECE", "movq -826366247(%r11), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r12), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r12), w_rdi), "498BBC24D9A6BECE", "movq -826366247(%r12), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r13), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r13), w_rdi), "498BBDD9A6BECE", "movq -826366247(%r13), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r14), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r14), w_rdi), "498BBED9A6BECE", "movq -826366247(%r14), %rdi", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r15), w_rdi, None), + Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r15), w_rdi), "498BBFD9A6BECE", "movq -826366247(%r15), %rdi", )); @@ -683,42 +683,42 @@ fn test_x64_emit() { // // Addr_IRRS, offset max simm8 insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, rax, rax, 0), w_r11, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, rax, rax, 0), w_r11), "4C8B5C007F", "movq 127(%rax,%rax,1), %r11", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, rdi, rax, 1), w_r11, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, rdi, rax, 1), w_r11), "4C8B5C477F", "movq 127(%rdi,%rax,2), %r11", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, r8, rax, 2), w_r11, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, r8, rax, 2), w_r11), "4D8B5C807F", "movq 127(%r8,%rax,4), %r11", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, r15, rax, 3), w_r11, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, r15, rax, 3), w_r11), "4D8B5CC77F", "movq 127(%r15,%rax,8), %r11", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, rax, rdi, 3), w_r11, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, rax, rdi, 3), w_r11), "4C8B5CF87F", "movq 127(%rax,%rdi,8), %r11", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, rdi, rdi, 2), w_r11, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, rdi, rdi, 2), w_r11), "4C8B5CBF7F", "movq 127(%rdi,%rdi,4), %r11", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, r8, rdi, 1), w_r11, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, r8, rdi, 1), w_r11), "4D8B5C787F", "movq 127(%r8,%rdi,2), %r11", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, r15, rdi, 0), w_r11, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(127, r15, rdi, 0), w_r11), "4D8B5C3F7F", "movq 127(%r15,%rdi,1), %r11", )); @@ -726,74 +726,42 @@ fn test_x64_emit() { // ======================================================== // Addr_IRRS, offset min simm8 insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(-128i32 as u32, rax, r8, 2), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(-128i32 as u32, rax, r8, 2), w_r11), "4E8B5C8080", "movq -128(%rax,%r8,4), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(-128i32 as u32, rdi, r8, 3), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(-128i32 as u32, rdi, r8, 3), w_r11), "4E8B5CC780", "movq -128(%rdi,%r8,8), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(-128i32 as u32, r8, r8, 0), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(-128i32 as u32, r8, r8, 0), w_r11), "4F8B5C0080", "movq -128(%r8,%r8,1), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(-128i32 as u32, r15, r8, 1), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(-128i32 as u32, r15, r8, 1), w_r11), "4F8B5C4780", "movq -128(%r15,%r8,2), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(-128i32 as u32, rax, r15, 1), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(-128i32 as u32, rax, r15, 1), w_r11), "4E8B5C7880", "movq -128(%rax,%r15,2), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(-128i32 as u32, rdi, r15, 0), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(-128i32 as u32, rdi, r15, 0), w_r11), "4E8B5C3F80", "movq -128(%rdi,%r15,1), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(-128i32 as u32, r8, r15, 3), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(-128i32 as u32, r8, r15, 3), w_r11), "4F8B5CF880", "movq -128(%r8,%r15,8), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(-128i32 as u32, r15, r15, 2), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(-128i32 as u32, r15, r15, 2), w_r11), "4F8B5CBF80", "movq -128(%r15,%r15,4), %r11", )); @@ -801,74 +769,42 @@ fn test_x64_emit() { // ======================================================== // Addr_IRRS, offset large positive simm32 insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(0x4f6625be, rax, rax, 0), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(0x4f6625be, rax, rax, 0), w_r11), "4C8B9C00BE25664F", "movq 1332094398(%rax,%rax,1), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(0x4f6625be, rdi, rax, 1), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(0x4f6625be, rdi, rax, 1), w_r11), "4C8B9C47BE25664F", "movq 1332094398(%rdi,%rax,2), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(0x4f6625be, r8, rax, 2), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(0x4f6625be, r8, rax, 2), w_r11), "4D8B9C80BE25664F", "movq 1332094398(%r8,%rax,4), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(0x4f6625be, r15, rax, 3), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(0x4f6625be, r15, rax, 3), w_r11), "4D8B9CC7BE25664F", "movq 1332094398(%r15,%rax,8), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(0x4f6625be, rax, rdi, 3), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(0x4f6625be, rax, rdi, 3), w_r11), "4C8B9CF8BE25664F", "movq 1332094398(%rax,%rdi,8), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(0x4f6625be, rdi, rdi, 2), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(0x4f6625be, rdi, rdi, 2), w_r11), "4C8B9CBFBE25664F", "movq 1332094398(%rdi,%rdi,4), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(0x4f6625be, r8, rdi, 1), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(0x4f6625be, r8, rdi, 1), w_r11), "4D8B9C78BE25664F", "movq 1332094398(%r8,%rdi,2), %r11", )); insns.push(( - Inst::mov64_m_r( - Amode::imm_reg_reg_shift(0x4f6625be, r15, rdi, 0), - w_r11, - None, - ), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(0x4f6625be, r15, rdi, 0), w_r11), "4D8B9C3FBE25664F", "movq 1332094398(%r15,%rdi,1), %r11", )); @@ -879,7 +815,6 @@ fn test_x64_emit() { Inst::mov64_m_r( Amode::imm_reg_reg_shift(-0x264d1690i32 as u32, rax, r8, 2), w_r11, - None, ), "4E8B9C8070E9B2D9", "movq -642586256(%rax,%r8,4), %r11", @@ -888,7 +823,6 @@ fn test_x64_emit() { Inst::mov64_m_r( Amode::imm_reg_reg_shift(-0x264d1690i32 as u32, rdi, r8, 3), w_r11, - None, ), "4E8B9CC770E9B2D9", "movq -642586256(%rdi,%r8,8), %r11", @@ -897,7 +831,6 @@ fn test_x64_emit() { Inst::mov64_m_r( Amode::imm_reg_reg_shift(-0x264d1690i32 as u32, r8, r8, 0), w_r11, - None, ), "4F8B9C0070E9B2D9", "movq -642586256(%r8,%r8,1), %r11", @@ -906,7 +839,6 @@ fn test_x64_emit() { Inst::mov64_m_r( Amode::imm_reg_reg_shift(-0x264d1690i32 as u32, r15, r8, 1), w_r11, - None, ), "4F8B9C4770E9B2D9", "movq -642586256(%r15,%r8,2), %r11", @@ -915,7 +847,6 @@ fn test_x64_emit() { Inst::mov64_m_r( Amode::imm_reg_reg_shift(-0x264d1690i32 as u32, rax, r15, 1), w_r11, - None, ), "4E8B9C7870E9B2D9", "movq -642586256(%rax,%r15,2), %r11", @@ -924,7 +855,6 @@ fn test_x64_emit() { Inst::mov64_m_r( Amode::imm_reg_reg_shift(-0x264d1690i32 as u32, rdi, r15, 0), w_r11, - None, ), "4E8B9C3F70E9B2D9", "movq -642586256(%rdi,%r15,1), %r11", @@ -933,7 +863,6 @@ fn test_x64_emit() { Inst::mov64_m_r( Amode::imm_reg_reg_shift(-0x264d1690i32 as u32, r8, r15, 3), w_r11, - None, ), "4F8B9CF870E9B2D9", "movq -642586256(%r8,%r15,8), %r11", @@ -942,7 +871,6 @@ fn test_x64_emit() { Inst::mov64_m_r( Amode::imm_reg_reg_shift(-0x264d1690i32 as u32, r15, r15, 2), w_r11, - None, ), "4F8B9CBF70E9B2D9", "movq -642586256(%r15,%r15,4), %r11", @@ -1292,42 +1220,22 @@ fn test_x64_emit() { // ======================================================== // Div insns.push(( - Inst::div( - 4, - true, /*signed*/ - RegMem::reg(regs::rsi()), - SourceLoc::default(), - ), + Inst::div(4, true /*signed*/, RegMem::reg(regs::rsi())), "F7FE", "idiv %esi", )); insns.push(( - Inst::div( - 8, - true, /*signed*/ - RegMem::reg(regs::r15()), - SourceLoc::default(), - ), + Inst::div(8, true /*signed*/, RegMem::reg(regs::r15())), "49F7FF", "idiv %r15", )); insns.push(( - Inst::div( - 4, - false, /*signed*/ - RegMem::reg(regs::r14()), - SourceLoc::default(), - ), + Inst::div(4, false /*signed*/, RegMem::reg(regs::r14())), "41F7F6", "div %r14d", )); insns.push(( - Inst::div( - 8, - false, /*signed*/ - RegMem::reg(regs::rdi()), - SourceLoc::default(), - ), + Inst::div(8, false /*signed*/, RegMem::reg(regs::rdi())), "48F7F7", "div %rdi", )); @@ -1455,17 +1363,17 @@ fn test_x64_emit() { // ======================================================== // MovZX_RM_R insns.push(( - Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(rdi), w_rdi, None), + Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(rdi), w_rdi), "400FB6FF", "movzbl %dil, %edi", )); insns.push(( - Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(rax), w_rsi, None), + Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(rax), w_rsi), "0FB6F0", "movzbl %al, %esi", )); insns.push(( - Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(r15), w_rsi, None), + Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(r15), w_rsi), "410FB6F7", "movzbl %r15b, %esi", )); @@ -1474,7 +1382,6 @@ fn test_x64_emit() { ExtMode::BL, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "0FB671F9", "movzbl -7(%rcx), %esi", @@ -1484,7 +1391,6 @@ fn test_x64_emit() { ExtMode::BL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "410FB658F9", "movzbl -7(%r8), %ebx", @@ -1494,7 +1400,6 @@ fn test_x64_emit() { ExtMode::BL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "450FB64AF9", "movzbl -7(%r10), %r9d", @@ -1504,18 +1409,17 @@ fn test_x64_emit() { ExtMode::BL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "410FB653F9", "movzbl -7(%r11), %edx", )); insns.push(( - Inst::movzx_rm_r(ExtMode::BQ, RegMem::reg(rax), w_rsi, None), + Inst::movzx_rm_r(ExtMode::BQ, RegMem::reg(rax), w_rsi), "480FB6F0", "movzbq %al, %rsi", )); insns.push(( - Inst::movzx_rm_r(ExtMode::BQ, RegMem::reg(r10), w_rsi, None), + Inst::movzx_rm_r(ExtMode::BQ, RegMem::reg(r10), w_rsi), "490FB6F2", "movzbq %r10b, %rsi", )); @@ -1524,7 +1428,6 @@ fn test_x64_emit() { ExtMode::BQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "480FB671F9", "movzbq -7(%rcx), %rsi", @@ -1534,7 +1437,6 @@ fn test_x64_emit() { ExtMode::BQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "490FB658F9", "movzbq -7(%r8), %rbx", @@ -1544,7 +1446,6 @@ fn test_x64_emit() { ExtMode::BQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "4D0FB64AF9", "movzbq -7(%r10), %r9", @@ -1554,18 +1455,17 @@ fn test_x64_emit() { ExtMode::BQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "490FB653F9", "movzbq -7(%r11), %rdx", )); insns.push(( - Inst::movzx_rm_r(ExtMode::WL, RegMem::reg(rcx), w_rsi, None), + Inst::movzx_rm_r(ExtMode::WL, RegMem::reg(rcx), w_rsi), "0FB7F1", "movzwl %cx, %esi", )); insns.push(( - Inst::movzx_rm_r(ExtMode::WL, RegMem::reg(r10), w_rsi, None), + Inst::movzx_rm_r(ExtMode::WL, RegMem::reg(r10), w_rsi), "410FB7F2", "movzwl %r10w, %esi", )); @@ -1574,7 +1474,6 @@ fn test_x64_emit() { ExtMode::WL, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "0FB771F9", "movzwl -7(%rcx), %esi", @@ -1584,7 +1483,6 @@ fn test_x64_emit() { ExtMode::WL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "410FB758F9", "movzwl -7(%r8), %ebx", @@ -1594,7 +1492,6 @@ fn test_x64_emit() { ExtMode::WL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "450FB74AF9", "movzwl -7(%r10), %r9d", @@ -1604,18 +1501,17 @@ fn test_x64_emit() { ExtMode::WL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "410FB753F9", "movzwl -7(%r11), %edx", )); insns.push(( - Inst::movzx_rm_r(ExtMode::WQ, RegMem::reg(rcx), w_rsi, None), + Inst::movzx_rm_r(ExtMode::WQ, RegMem::reg(rcx), w_rsi), "480FB7F1", "movzwq %cx, %rsi", )); insns.push(( - Inst::movzx_rm_r(ExtMode::WQ, RegMem::reg(r11), w_rsi, None), + Inst::movzx_rm_r(ExtMode::WQ, RegMem::reg(r11), w_rsi), "490FB7F3", "movzwq %r11w, %rsi", )); @@ -1624,7 +1520,6 @@ fn test_x64_emit() { ExtMode::WQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "480FB771F9", "movzwq -7(%rcx), %rsi", @@ -1634,7 +1529,6 @@ fn test_x64_emit() { ExtMode::WQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "490FB758F9", "movzwq -7(%r8), %rbx", @@ -1644,7 +1538,6 @@ fn test_x64_emit() { ExtMode::WQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "4D0FB74AF9", "movzwq -7(%r10), %r9", @@ -1654,13 +1547,12 @@ fn test_x64_emit() { ExtMode::WQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "490FB753F9", "movzwq -7(%r11), %rdx", )); insns.push(( - Inst::movzx_rm_r(ExtMode::LQ, RegMem::reg(rcx), w_rsi, None), + Inst::movzx_rm_r(ExtMode::LQ, RegMem::reg(rcx), w_rsi), "8BF1", "movl %ecx, %esi", )); @@ -1669,7 +1561,6 @@ fn test_x64_emit() { ExtMode::LQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "8B71F9", "movl -7(%rcx), %esi", @@ -1679,7 +1570,6 @@ fn test_x64_emit() { ExtMode::LQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "418B58F9", "movl -7(%r8), %ebx", @@ -1689,7 +1579,6 @@ fn test_x64_emit() { ExtMode::LQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "458B4AF9", "movl -7(%r10), %r9d", @@ -1699,7 +1588,6 @@ fn test_x64_emit() { ExtMode::LQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "418B53F9", "movl -7(%r11), %edx", @@ -1708,42 +1596,42 @@ fn test_x64_emit() { // ======================================================== // Mov64_M_R insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, rax, rbx, 0), w_rcx, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, rax, rbx, 0), w_rcx), "488B8C18B3000000", "movq 179(%rax,%rbx,1), %rcx", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, rax, rbx, 0), w_r8, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, rax, rbx, 0), w_r8), "4C8B8418B3000000", "movq 179(%rax,%rbx,1), %r8", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, rax, r9, 0), w_rcx, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, rax, r9, 0), w_rcx), "4A8B8C08B3000000", "movq 179(%rax,%r9,1), %rcx", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, rax, r9, 0), w_r8, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, rax, r9, 0), w_r8), "4E8B8408B3000000", "movq 179(%rax,%r9,1), %r8", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, r10, rbx, 0), w_rcx, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, r10, rbx, 0), w_rcx), "498B8C1AB3000000", "movq 179(%r10,%rbx,1), %rcx", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, r10, rbx, 0), w_r8, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, r10, rbx, 0), w_r8), "4D8B841AB3000000", "movq 179(%r10,%rbx,1), %r8", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, r10, r9, 0), w_rcx, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, r10, r9, 0), w_rcx), "4B8B8C0AB3000000", "movq 179(%r10,%r9,1), %rcx", )); insns.push(( - Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, r10, r9, 0), w_r8, None), + Inst::mov64_m_r(Amode::imm_reg_reg_shift(179, r10, r9, 0), w_r8), "4F8B840AB3000000", "movq 179(%r10,%r9,1), %r8", )); @@ -1774,17 +1662,17 @@ fn test_x64_emit() { // ======================================================== // MovSX_RM_R insns.push(( - Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rdi), w_rdi, None), + Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rdi), w_rdi), "400FBEFF", "movsbl %dil, %edi", )); insns.push(( - Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rcx), w_rsi, None), + Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rcx), w_rsi), "0FBEF1", "movsbl %cl, %esi", )); insns.push(( - Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(r14), w_rsi, None), + Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(r14), w_rsi), "410FBEF6", "movsbl %r14b, %esi", )); @@ -1793,7 +1681,6 @@ fn test_x64_emit() { ExtMode::BL, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "0FBE71F9", "movsbl -7(%rcx), %esi", @@ -1803,7 +1690,6 @@ fn test_x64_emit() { ExtMode::BL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "410FBE58F9", "movsbl -7(%r8), %ebx", @@ -1813,7 +1699,6 @@ fn test_x64_emit() { ExtMode::BL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "450FBE4AF9", "movsbl -7(%r10), %r9d", @@ -1823,18 +1708,17 @@ fn test_x64_emit() { ExtMode::BL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "410FBE53F9", "movsbl -7(%r11), %edx", )); insns.push(( - Inst::movsx_rm_r(ExtMode::BQ, RegMem::reg(rcx), w_rsi, None), + Inst::movsx_rm_r(ExtMode::BQ, RegMem::reg(rcx), w_rsi), "480FBEF1", "movsbq %cl, %rsi", )); insns.push(( - Inst::movsx_rm_r(ExtMode::BQ, RegMem::reg(r15), w_rsi, None), + Inst::movsx_rm_r(ExtMode::BQ, RegMem::reg(r15), w_rsi), "490FBEF7", "movsbq %r15b, %rsi", )); @@ -1843,7 +1727,6 @@ fn test_x64_emit() { ExtMode::BQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "480FBE71F9", "movsbq -7(%rcx), %rsi", @@ -1853,7 +1736,6 @@ fn test_x64_emit() { ExtMode::BQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "490FBE58F9", "movsbq -7(%r8), %rbx", @@ -1863,7 +1745,6 @@ fn test_x64_emit() { ExtMode::BQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "4D0FBE4AF9", "movsbq -7(%r10), %r9", @@ -1873,18 +1754,17 @@ fn test_x64_emit() { ExtMode::BQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "490FBE53F9", "movsbq -7(%r11), %rdx", )); insns.push(( - Inst::movsx_rm_r(ExtMode::WL, RegMem::reg(rcx), w_rsi, None), + Inst::movsx_rm_r(ExtMode::WL, RegMem::reg(rcx), w_rsi), "0FBFF1", "movswl %cx, %esi", )); insns.push(( - Inst::movsx_rm_r(ExtMode::WL, RegMem::reg(r14), w_rsi, None), + Inst::movsx_rm_r(ExtMode::WL, RegMem::reg(r14), w_rsi), "410FBFF6", "movswl %r14w, %esi", )); @@ -1893,7 +1773,6 @@ fn test_x64_emit() { ExtMode::WL, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "0FBF71F9", "movswl -7(%rcx), %esi", @@ -1903,7 +1782,6 @@ fn test_x64_emit() { ExtMode::WL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "410FBF58F9", "movswl -7(%r8), %ebx", @@ -1913,7 +1791,6 @@ fn test_x64_emit() { ExtMode::WL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "450FBF4AF9", "movswl -7(%r10), %r9d", @@ -1923,18 +1800,17 @@ fn test_x64_emit() { ExtMode::WL, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "410FBF53F9", "movswl -7(%r11), %edx", )); insns.push(( - Inst::movsx_rm_r(ExtMode::WQ, RegMem::reg(rcx), w_rsi, None), + Inst::movsx_rm_r(ExtMode::WQ, RegMem::reg(rcx), w_rsi), "480FBFF1", "movswq %cx, %rsi", )); insns.push(( - Inst::movsx_rm_r(ExtMode::WQ, RegMem::reg(r13), w_rsi, None), + Inst::movsx_rm_r(ExtMode::WQ, RegMem::reg(r13), w_rsi), "490FBFF5", "movswq %r13w, %rsi", )); @@ -1943,7 +1819,6 @@ fn test_x64_emit() { ExtMode::WQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "480FBF71F9", "movswq -7(%rcx), %rsi", @@ -1953,7 +1828,6 @@ fn test_x64_emit() { ExtMode::WQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "490FBF58F9", "movswq -7(%r8), %rbx", @@ -1963,7 +1837,6 @@ fn test_x64_emit() { ExtMode::WQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "4D0FBF4AF9", "movswq -7(%r10), %r9", @@ -1973,18 +1846,17 @@ fn test_x64_emit() { ExtMode::WQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "490FBF53F9", "movswq -7(%r11), %rdx", )); insns.push(( - Inst::movsx_rm_r(ExtMode::LQ, RegMem::reg(rcx), w_rsi, None), + Inst::movsx_rm_r(ExtMode::LQ, RegMem::reg(rcx), w_rsi), "4863F1", "movslq %ecx, %rsi", )); insns.push(( - Inst::movsx_rm_r(ExtMode::LQ, RegMem::reg(r15), w_rsi, None), + Inst::movsx_rm_r(ExtMode::LQ, RegMem::reg(r15), w_rsi), "4963F7", "movslq %r15d, %rsi", )); @@ -1993,7 +1865,6 @@ fn test_x64_emit() { ExtMode::LQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)), w_rsi, - None, ), "486371F9", "movslq -7(%rcx), %rsi", @@ -2003,7 +1874,6 @@ fn test_x64_emit() { ExtMode::LQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)), w_rbx, - None, ), "496358F9", "movslq -7(%r8), %rbx", @@ -2013,7 +1883,6 @@ fn test_x64_emit() { ExtMode::LQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)), w_r9, - None, ), "4D634AF9", "movslq -7(%r10), %r9", @@ -2023,7 +1892,6 @@ fn test_x64_emit() { ExtMode::LQ, RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)), w_rdx, - None, ), "496353F9", "movslq -7(%r11), %rdx", @@ -2032,325 +1900,325 @@ fn test_x64_emit() { // ======================================================== // Mov_R_M. Byte stores are tricky. Check everything carefully. insns.push(( - Inst::mov_r_m(8, rax, Amode::imm_reg(99, rdi), None), + Inst::mov_r_m(8, rax, Amode::imm_reg(99, rdi)), "48894763", "movq %rax, 99(%rdi)", )); insns.push(( - Inst::mov_r_m(8, rbx, Amode::imm_reg(99, r8), None), + Inst::mov_r_m(8, rbx, Amode::imm_reg(99, r8)), "49895863", "movq %rbx, 99(%r8)", )); insns.push(( - Inst::mov_r_m(8, rcx, Amode::imm_reg(99, rsi), None), + Inst::mov_r_m(8, rcx, Amode::imm_reg(99, rsi)), "48894E63", "movq %rcx, 99(%rsi)", )); insns.push(( - Inst::mov_r_m(8, rdx, Amode::imm_reg(99, r9), None), + Inst::mov_r_m(8, rdx, Amode::imm_reg(99, r9)), "49895163", "movq %rdx, 99(%r9)", )); insns.push(( - Inst::mov_r_m(8, rsi, Amode::imm_reg(99, rax), None), + Inst::mov_r_m(8, rsi, Amode::imm_reg(99, rax)), "48897063", "movq %rsi, 99(%rax)", )); insns.push(( - Inst::mov_r_m(8, rdi, Amode::imm_reg(99, r15), None), + Inst::mov_r_m(8, rdi, Amode::imm_reg(99, r15)), "49897F63", "movq %rdi, 99(%r15)", )); insns.push(( - Inst::mov_r_m(8, rsp, Amode::imm_reg(99, rcx), None), + Inst::mov_r_m(8, rsp, Amode::imm_reg(99, rcx)), "48896163", "movq %rsp, 99(%rcx)", )); insns.push(( - Inst::mov_r_m(8, rbp, Amode::imm_reg(99, r14), None), + Inst::mov_r_m(8, rbp, Amode::imm_reg(99, r14)), "49896E63", "movq %rbp, 99(%r14)", )); insns.push(( - Inst::mov_r_m(8, r8, Amode::imm_reg(99, rdi), None), + Inst::mov_r_m(8, r8, Amode::imm_reg(99, rdi)), "4C894763", "movq %r8, 99(%rdi)", )); insns.push(( - Inst::mov_r_m(8, r9, Amode::imm_reg(99, r8), None), + Inst::mov_r_m(8, r9, Amode::imm_reg(99, r8)), "4D894863", "movq %r9, 99(%r8)", )); insns.push(( - Inst::mov_r_m(8, r10, Amode::imm_reg(99, rsi), None), + Inst::mov_r_m(8, r10, Amode::imm_reg(99, rsi)), "4C895663", "movq %r10, 99(%rsi)", )); insns.push(( - Inst::mov_r_m(8, r11, Amode::imm_reg(99, r9), None), + Inst::mov_r_m(8, r11, Amode::imm_reg(99, r9)), "4D895963", "movq %r11, 99(%r9)", )); insns.push(( - Inst::mov_r_m(8, r12, Amode::imm_reg(99, rax), None), + Inst::mov_r_m(8, r12, Amode::imm_reg(99, rax)), "4C896063", "movq %r12, 99(%rax)", )); insns.push(( - Inst::mov_r_m(8, r13, Amode::imm_reg(99, r15), None), + Inst::mov_r_m(8, r13, Amode::imm_reg(99, r15)), "4D896F63", "movq %r13, 99(%r15)", )); insns.push(( - Inst::mov_r_m(8, r14, Amode::imm_reg(99, rcx), None), + Inst::mov_r_m(8, r14, Amode::imm_reg(99, rcx)), "4C897163", "movq %r14, 99(%rcx)", )); insns.push(( - Inst::mov_r_m(8, r15, Amode::imm_reg(99, r14), None), + Inst::mov_r_m(8, r15, Amode::imm_reg(99, r14)), "4D897E63", "movq %r15, 99(%r14)", )); // insns.push(( - Inst::mov_r_m(4, rax, Amode::imm_reg(99, rdi), None), + Inst::mov_r_m(4, rax, Amode::imm_reg(99, rdi)), "894763", "movl %eax, 99(%rdi)", )); insns.push(( - Inst::mov_r_m(4, rbx, Amode::imm_reg(99, r8), None), + Inst::mov_r_m(4, rbx, Amode::imm_reg(99, r8)), "41895863", "movl %ebx, 99(%r8)", )); insns.push(( - Inst::mov_r_m(4, rcx, Amode::imm_reg(99, rsi), None), + Inst::mov_r_m(4, rcx, Amode::imm_reg(99, rsi)), "894E63", "movl %ecx, 99(%rsi)", )); insns.push(( - Inst::mov_r_m(4, rdx, Amode::imm_reg(99, r9), None), + Inst::mov_r_m(4, rdx, Amode::imm_reg(99, r9)), "41895163", "movl %edx, 99(%r9)", )); insns.push(( - Inst::mov_r_m(4, rsi, Amode::imm_reg(99, rax), None), + Inst::mov_r_m(4, rsi, Amode::imm_reg(99, rax)), "897063", "movl %esi, 99(%rax)", )); insns.push(( - Inst::mov_r_m(4, rdi, Amode::imm_reg(99, r15), None), + Inst::mov_r_m(4, rdi, Amode::imm_reg(99, r15)), "41897F63", "movl %edi, 99(%r15)", )); insns.push(( - Inst::mov_r_m(4, rsp, Amode::imm_reg(99, rcx), None), + Inst::mov_r_m(4, rsp, Amode::imm_reg(99, rcx)), "896163", "movl %esp, 99(%rcx)", )); insns.push(( - Inst::mov_r_m(4, rbp, Amode::imm_reg(99, r14), None), + Inst::mov_r_m(4, rbp, Amode::imm_reg(99, r14)), "41896E63", "movl %ebp, 99(%r14)", )); insns.push(( - Inst::mov_r_m(4, r8, Amode::imm_reg(99, rdi), None), + Inst::mov_r_m(4, r8, Amode::imm_reg(99, rdi)), "44894763", "movl %r8d, 99(%rdi)", )); insns.push(( - Inst::mov_r_m(4, r9, Amode::imm_reg(99, r8), None), + Inst::mov_r_m(4, r9, Amode::imm_reg(99, r8)), "45894863", "movl %r9d, 99(%r8)", )); insns.push(( - Inst::mov_r_m(4, r10, Amode::imm_reg(99, rsi), None), + Inst::mov_r_m(4, r10, Amode::imm_reg(99, rsi)), "44895663", "movl %r10d, 99(%rsi)", )); insns.push(( - Inst::mov_r_m(4, r11, Amode::imm_reg(99, r9), None), + Inst::mov_r_m(4, r11, Amode::imm_reg(99, r9)), "45895963", "movl %r11d, 99(%r9)", )); insns.push(( - Inst::mov_r_m(4, r12, Amode::imm_reg(99, rax), None), + Inst::mov_r_m(4, r12, Amode::imm_reg(99, rax)), "44896063", "movl %r12d, 99(%rax)", )); insns.push(( - Inst::mov_r_m(4, r13, Amode::imm_reg(99, r15), None), + Inst::mov_r_m(4, r13, Amode::imm_reg(99, r15)), "45896F63", "movl %r13d, 99(%r15)", )); insns.push(( - Inst::mov_r_m(4, r14, Amode::imm_reg(99, rcx), None), + Inst::mov_r_m(4, r14, Amode::imm_reg(99, rcx)), "44897163", "movl %r14d, 99(%rcx)", )); insns.push(( - Inst::mov_r_m(4, r15, Amode::imm_reg(99, r14), None), + Inst::mov_r_m(4, r15, Amode::imm_reg(99, r14)), "45897E63", "movl %r15d, 99(%r14)", )); // insns.push(( - Inst::mov_r_m(2, rax, Amode::imm_reg(99, rdi), None), + Inst::mov_r_m(2, rax, Amode::imm_reg(99, rdi)), "66894763", "movw %ax, 99(%rdi)", )); insns.push(( - Inst::mov_r_m(2, rbx, Amode::imm_reg(99, r8), None), + Inst::mov_r_m(2, rbx, Amode::imm_reg(99, r8)), "6641895863", "movw %bx, 99(%r8)", )); insns.push(( - Inst::mov_r_m(2, rcx, Amode::imm_reg(99, rsi), None), + Inst::mov_r_m(2, rcx, Amode::imm_reg(99, rsi)), "66894E63", "movw %cx, 99(%rsi)", )); insns.push(( - Inst::mov_r_m(2, rdx, Amode::imm_reg(99, r9), None), + Inst::mov_r_m(2, rdx, Amode::imm_reg(99, r9)), "6641895163", "movw %dx, 99(%r9)", )); insns.push(( - Inst::mov_r_m(2, rsi, Amode::imm_reg(99, rax), None), + Inst::mov_r_m(2, rsi, Amode::imm_reg(99, rax)), "66897063", "movw %si, 99(%rax)", )); insns.push(( - Inst::mov_r_m(2, rdi, Amode::imm_reg(99, r15), None), + Inst::mov_r_m(2, rdi, Amode::imm_reg(99, r15)), "6641897F63", "movw %di, 99(%r15)", )); insns.push(( - Inst::mov_r_m(2, rsp, Amode::imm_reg(99, rcx), None), + Inst::mov_r_m(2, rsp, Amode::imm_reg(99, rcx)), "66896163", "movw %sp, 99(%rcx)", )); insns.push(( - Inst::mov_r_m(2, rbp, Amode::imm_reg(99, r14), None), + Inst::mov_r_m(2, rbp, Amode::imm_reg(99, r14)), "6641896E63", "movw %bp, 99(%r14)", )); insns.push(( - Inst::mov_r_m(2, r8, Amode::imm_reg(99, rdi), None), + Inst::mov_r_m(2, r8, Amode::imm_reg(99, rdi)), "6644894763", "movw %r8w, 99(%rdi)", )); insns.push(( - Inst::mov_r_m(2, r9, Amode::imm_reg(99, r8), None), + Inst::mov_r_m(2, r9, Amode::imm_reg(99, r8)), "6645894863", "movw %r9w, 99(%r8)", )); insns.push(( - Inst::mov_r_m(2, r10, Amode::imm_reg(99, rsi), None), + Inst::mov_r_m(2, r10, Amode::imm_reg(99, rsi)), "6644895663", "movw %r10w, 99(%rsi)", )); insns.push(( - Inst::mov_r_m(2, r11, Amode::imm_reg(99, r9), None), + Inst::mov_r_m(2, r11, Amode::imm_reg(99, r9)), "6645895963", "movw %r11w, 99(%r9)", )); insns.push(( - Inst::mov_r_m(2, r12, Amode::imm_reg(99, rax), None), + Inst::mov_r_m(2, r12, Amode::imm_reg(99, rax)), "6644896063", "movw %r12w, 99(%rax)", )); insns.push(( - Inst::mov_r_m(2, r13, Amode::imm_reg(99, r15), None), + Inst::mov_r_m(2, r13, Amode::imm_reg(99, r15)), "6645896F63", "movw %r13w, 99(%r15)", )); insns.push(( - Inst::mov_r_m(2, r14, Amode::imm_reg(99, rcx), None), + Inst::mov_r_m(2, r14, Amode::imm_reg(99, rcx)), "6644897163", "movw %r14w, 99(%rcx)", )); insns.push(( - Inst::mov_r_m(2, r15, Amode::imm_reg(99, r14), None), + Inst::mov_r_m(2, r15, Amode::imm_reg(99, r14)), "6645897E63", "movw %r15w, 99(%r14)", )); // insns.push(( - Inst::mov_r_m(1, rax, Amode::imm_reg(99, rdi), None), + Inst::mov_r_m(1, rax, Amode::imm_reg(99, rdi)), "884763", "movb %al, 99(%rdi)", )); insns.push(( - Inst::mov_r_m(1, rbx, Amode::imm_reg(99, r8), None), + Inst::mov_r_m(1, rbx, Amode::imm_reg(99, r8)), "41885863", "movb %bl, 99(%r8)", )); insns.push(( - Inst::mov_r_m(1, rcx, Amode::imm_reg(99, rsi), None), + Inst::mov_r_m(1, rcx, Amode::imm_reg(99, rsi)), "884E63", "movb %cl, 99(%rsi)", )); insns.push(( - Inst::mov_r_m(1, rdx, Amode::imm_reg(99, r9), None), + Inst::mov_r_m(1, rdx, Amode::imm_reg(99, r9)), "41885163", "movb %dl, 99(%r9)", )); insns.push(( - Inst::mov_r_m(1, rsi, Amode::imm_reg(99, rax), None), + Inst::mov_r_m(1, rsi, Amode::imm_reg(99, rax)), "40887063", "movb %sil, 99(%rax)", )); insns.push(( - Inst::mov_r_m(1, rdi, Amode::imm_reg(99, r15), None), + Inst::mov_r_m(1, rdi, Amode::imm_reg(99, r15)), "41887F63", "movb %dil, 99(%r15)", )); insns.push(( - Inst::mov_r_m(1, rsp, Amode::imm_reg(99, rcx), None), + Inst::mov_r_m(1, rsp, Amode::imm_reg(99, rcx)), "40886163", "movb %spl, 99(%rcx)", )); insns.push(( - Inst::mov_r_m(1, rbp, Amode::imm_reg(99, r14), None), + Inst::mov_r_m(1, rbp, Amode::imm_reg(99, r14)), "41886E63", "movb %bpl, 99(%r14)", )); insns.push(( - Inst::mov_r_m(1, r8, Amode::imm_reg(99, rdi), None), + Inst::mov_r_m(1, r8, Amode::imm_reg(99, rdi)), "44884763", "movb %r8b, 99(%rdi)", )); insns.push(( - Inst::mov_r_m(1, r9, Amode::imm_reg(99, r8), None), + Inst::mov_r_m(1, r9, Amode::imm_reg(99, r8)), "45884863", "movb %r9b, 99(%r8)", )); insns.push(( - Inst::mov_r_m(1, r10, Amode::imm_reg(99, rsi), None), + Inst::mov_r_m(1, r10, Amode::imm_reg(99, rsi)), "44885663", "movb %r10b, 99(%rsi)", )); insns.push(( - Inst::mov_r_m(1, r11, Amode::imm_reg(99, r9), None), + Inst::mov_r_m(1, r11, Amode::imm_reg(99, r9)), "45885963", "movb %r11b, 99(%r9)", )); insns.push(( - Inst::mov_r_m(1, r12, Amode::imm_reg(99, rax), None), + Inst::mov_r_m(1, r12, Amode::imm_reg(99, rax)), "44886063", "movb %r12b, 99(%rax)", )); insns.push(( - Inst::mov_r_m(1, r13, Amode::imm_reg(99, r15), None), + Inst::mov_r_m(1, r13, Amode::imm_reg(99, r15)), "45886F63", "movb %r13b, 99(%r15)", )); insns.push(( - Inst::mov_r_m(1, r14, Amode::imm_reg(99, rcx), None), + Inst::mov_r_m(1, r14, Amode::imm_reg(99, rcx)), "44887163", "movb %r14b, 99(%rcx)", )); insns.push(( - Inst::mov_r_m(1, r15, Amode::imm_reg(99, r14), None), + Inst::mov_r_m(1, r15, Amode::imm_reg(99, r14)), "45887E63", "movb %r15b, 99(%r14)", )); @@ -2885,7 +2753,6 @@ fn test_x64_emit() { }, Vec::new(), Vec::new(), - SourceLoc::default(), Opcode::Call, ), "E800000000", @@ -2895,13 +2762,7 @@ fn test_x64_emit() { // ======================================================== // CallUnknown fn call_unknown(rm: RegMem) -> Inst { - Inst::call_unknown( - rm, - Vec::new(), - Vec::new(), - SourceLoc::default(), - Opcode::CallIndirect, - ) + Inst::call_unknown(rm, Vec::new(), Vec::new(), Opcode::CallIndirect) } insns.push((call_unknown(RegMem::reg(rbp)), "FFD5", "call *%rbp")); @@ -2983,12 +2844,12 @@ fn test_x64_emit() { // XMM_RM_R: float binary ops insns.push(( - Inst::xmm_rm_r(SseOpcode::Addss, RegMem::reg(xmm1), w_xmm0, None), + Inst::xmm_rm_r(SseOpcode::Addss, RegMem::reg(xmm1), w_xmm0), "F30F58C1", "addss %xmm1, %xmm0", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Addss, RegMem::reg(xmm11), w_xmm13, None), + Inst::xmm_rm_r(SseOpcode::Addss, RegMem::reg(xmm11), w_xmm13), "F3450F58EB", "addss %xmm11, %xmm13", )); @@ -2997,24 +2858,23 @@ fn test_x64_emit() { SseOpcode::Addss, RegMem::mem(Amode::imm_reg_reg_shift(123, r10, rdx, 2)), w_xmm0, - None, ), "F3410F5844927B", "addss 123(%r10,%rdx,4), %xmm0", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Addsd, RegMem::reg(xmm15), w_xmm4, None), + Inst::xmm_rm_r(SseOpcode::Addsd, RegMem::reg(xmm15), w_xmm4), "F2410F58E7", "addsd %xmm15, %xmm4", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Subss, RegMem::reg(xmm0), w_xmm1, None), + Inst::xmm_rm_r(SseOpcode::Subss, RegMem::reg(xmm0), w_xmm1), "F30F5CC8", "subss %xmm0, %xmm1", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Subss, RegMem::reg(xmm12), w_xmm1, None), + Inst::xmm_rm_r(SseOpcode::Subss, RegMem::reg(xmm12), w_xmm1), "F3410F5CCC", "subss %xmm12, %xmm1", )); @@ -3023,58 +2883,57 @@ fn test_x64_emit() { SseOpcode::Subss, RegMem::mem(Amode::imm_reg_reg_shift(321, r10, rax, 3)), w_xmm10, - None, ), "F3450F5C94C241010000", "subss 321(%r10,%rax,8), %xmm10", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Subsd, RegMem::reg(xmm5), w_xmm14, None), + Inst::xmm_rm_r(SseOpcode::Subsd, RegMem::reg(xmm5), w_xmm14), "F2440F5CF5", "subsd %xmm5, %xmm14", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Mulss, RegMem::reg(xmm5), w_xmm4, None), + Inst::xmm_rm_r(SseOpcode::Mulss, RegMem::reg(xmm5), w_xmm4), "F30F59E5", "mulss %xmm5, %xmm4", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Mulsd, RegMem::reg(xmm5), w_xmm4, None), + Inst::xmm_rm_r(SseOpcode::Mulsd, RegMem::reg(xmm5), w_xmm4), "F20F59E5", "mulsd %xmm5, %xmm4", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Divss, RegMem::reg(xmm8), w_xmm7, None), + Inst::xmm_rm_r(SseOpcode::Divss, RegMem::reg(xmm8), w_xmm7), "F3410F5EF8", "divss %xmm8, %xmm7", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Divsd, RegMem::reg(xmm5), w_xmm4, None), + Inst::xmm_rm_r(SseOpcode::Divsd, RegMem::reg(xmm5), w_xmm4), "F20F5EE5", "divsd %xmm5, %xmm4", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Andps, RegMem::reg(xmm3), w_xmm12, None), + Inst::xmm_rm_r(SseOpcode::Andps, RegMem::reg(xmm3), w_xmm12), "440F54E3", "andps %xmm3, %xmm12", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Andnps, RegMem::reg(xmm4), w_xmm11, None), + Inst::xmm_rm_r(SseOpcode::Andnps, RegMem::reg(xmm4), w_xmm11), "440F55DC", "andnps %xmm4, %xmm11", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm1), w_xmm15, None), + Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm1), w_xmm15), "440F56F9", "orps %xmm1, %xmm15", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm5), w_xmm4, None), + Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm5), w_xmm4), "0F56E5", "orps %xmm5, %xmm4", )); @@ -3083,217 +2942,217 @@ fn test_x64_emit() { // XMM_RM_R: Integer Packed insns.push(( - Inst::xmm_rm_r(SseOpcode::Paddb, RegMem::reg(xmm9), w_xmm5, None), + Inst::xmm_rm_r(SseOpcode::Paddb, RegMem::reg(xmm9), w_xmm5), "66410FFCE9", "paddb %xmm9, %xmm5", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Paddw, RegMem::reg(xmm7), w_xmm6, None), + Inst::xmm_rm_r(SseOpcode::Paddw, RegMem::reg(xmm7), w_xmm6), "660FFDF7", "paddw %xmm7, %xmm6", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Paddd, RegMem::reg(xmm12), w_xmm13, None), + Inst::xmm_rm_r(SseOpcode::Paddd, RegMem::reg(xmm12), w_xmm13), "66450FFEEC", "paddd %xmm12, %xmm13", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Paddq, RegMem::reg(xmm1), w_xmm8, None), + Inst::xmm_rm_r(SseOpcode::Paddq, RegMem::reg(xmm1), w_xmm8), "66440FD4C1", "paddq %xmm1, %xmm8", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Paddsb, RegMem::reg(xmm9), w_xmm5, None), + Inst::xmm_rm_r(SseOpcode::Paddsb, RegMem::reg(xmm9), w_xmm5), "66410FECE9", "paddsb %xmm9, %xmm5", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Paddsw, RegMem::reg(xmm7), w_xmm6, None), + Inst::xmm_rm_r(SseOpcode::Paddsw, RegMem::reg(xmm7), w_xmm6), "660FEDF7", "paddsw %xmm7, %xmm6", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Paddusb, RegMem::reg(xmm12), w_xmm13, None), + Inst::xmm_rm_r(SseOpcode::Paddusb, RegMem::reg(xmm12), w_xmm13), "66450FDCEC", "paddusb %xmm12, %xmm13", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Paddusw, RegMem::reg(xmm1), w_xmm8, None), + Inst::xmm_rm_r(SseOpcode::Paddusw, RegMem::reg(xmm1), w_xmm8), "66440FDDC1", "paddusw %xmm1, %xmm8", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Psubsb, RegMem::reg(xmm9), w_xmm5, None), + Inst::xmm_rm_r(SseOpcode::Psubsb, RegMem::reg(xmm9), w_xmm5), "66410FE8E9", "psubsb %xmm9, %xmm5", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Psubsw, RegMem::reg(xmm7), w_xmm6, None), + Inst::xmm_rm_r(SseOpcode::Psubsw, RegMem::reg(xmm7), w_xmm6), "660FE9F7", "psubsw %xmm7, %xmm6", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Psubusb, RegMem::reg(xmm12), w_xmm13, None), + Inst::xmm_rm_r(SseOpcode::Psubusb, RegMem::reg(xmm12), w_xmm13), "66450FD8EC", "psubusb %xmm12, %xmm13", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Psubusw, RegMem::reg(xmm1), w_xmm8, None), + Inst::xmm_rm_r(SseOpcode::Psubusw, RegMem::reg(xmm1), w_xmm8), "66440FD9C1", "psubusw %xmm1, %xmm8", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pavgb, RegMem::reg(xmm12), w_xmm13, None), + Inst::xmm_rm_r(SseOpcode::Pavgb, RegMem::reg(xmm12), w_xmm13), "66450FE0EC", "pavgb %xmm12, %xmm13", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pavgw, RegMem::reg(xmm1), w_xmm8, None), + Inst::xmm_rm_r(SseOpcode::Pavgw, RegMem::reg(xmm1), w_xmm8), "66440FE3C1", "pavgw %xmm1, %xmm8", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Psubb, RegMem::reg(xmm5), w_xmm9, None), + Inst::xmm_rm_r(SseOpcode::Psubb, RegMem::reg(xmm5), w_xmm9), "66440FF8CD", "psubb %xmm5, %xmm9", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Psubw, RegMem::reg(xmm6), w_xmm7, None), + Inst::xmm_rm_r(SseOpcode::Psubw, RegMem::reg(xmm6), w_xmm7), "660FF9FE", "psubw %xmm6, %xmm7", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Psubd, RegMem::reg(xmm13), w_xmm12, None), + Inst::xmm_rm_r(SseOpcode::Psubd, RegMem::reg(xmm13), w_xmm12), "66450FFAE5", "psubd %xmm13, %xmm12", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Psubq, RegMem::reg(xmm8), w_xmm1, None), + Inst::xmm_rm_r(SseOpcode::Psubq, RegMem::reg(xmm8), w_xmm1), "66410FFBC8", "psubq %xmm8, %xmm1", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmulld, RegMem::reg(xmm15), w_xmm6, None), + Inst::xmm_rm_r(SseOpcode::Pmulld, RegMem::reg(xmm15), w_xmm6), "66410F3840F7", "pmulld %xmm15, %xmm6", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(xmm14), w_xmm1, None), + Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(xmm14), w_xmm1), "66410FD5CE", "pmullw %xmm14, %xmm1", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmuludq, RegMem::reg(xmm8), w_xmm9, None), + Inst::xmm_rm_r(SseOpcode::Pmuludq, RegMem::reg(xmm8), w_xmm9), "66450FF4C8", "pmuludq %xmm8, %xmm9", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmaxsb, RegMem::reg(xmm15), w_xmm6, None), + Inst::xmm_rm_r(SseOpcode::Pmaxsb, RegMem::reg(xmm15), w_xmm6), "66410F383CF7", "pmaxsb %xmm15, %xmm6", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmaxsw, RegMem::reg(xmm15), w_xmm6, None), + Inst::xmm_rm_r(SseOpcode::Pmaxsw, RegMem::reg(xmm15), w_xmm6), "66410FEEF7", "pmaxsw %xmm15, %xmm6", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmaxsd, RegMem::reg(xmm15), w_xmm6, None), + Inst::xmm_rm_r(SseOpcode::Pmaxsd, RegMem::reg(xmm15), w_xmm6), "66410F383DF7", "pmaxsd %xmm15, %xmm6", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmaxub, RegMem::reg(xmm14), w_xmm1, None), + Inst::xmm_rm_r(SseOpcode::Pmaxub, RegMem::reg(xmm14), w_xmm1), "66410FDECE", "pmaxub %xmm14, %xmm1", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmaxuw, RegMem::reg(xmm14), w_xmm1, None), + Inst::xmm_rm_r(SseOpcode::Pmaxuw, RegMem::reg(xmm14), w_xmm1), "66410F383ECE", "pmaxuw %xmm14, %xmm1", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pmaxud, RegMem::reg(xmm14), w_xmm1, None), + Inst::xmm_rm_r(SseOpcode::Pmaxud, RegMem::reg(xmm14), w_xmm1), "66410F383FCE", "pmaxud %xmm14, %xmm1", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pminsb, RegMem::reg(xmm8), w_xmm9, None), + Inst::xmm_rm_r(SseOpcode::Pminsb, RegMem::reg(xmm8), w_xmm9), "66450F3838C8", "pminsb %xmm8, %xmm9", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pminsw, RegMem::reg(xmm8), w_xmm9, None), + Inst::xmm_rm_r(SseOpcode::Pminsw, RegMem::reg(xmm8), w_xmm9), "66450FEAC8", "pminsw %xmm8, %xmm9", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pminsd, RegMem::reg(xmm8), w_xmm9, None), + Inst::xmm_rm_r(SseOpcode::Pminsd, RegMem::reg(xmm8), w_xmm9), "66450F3839C8", "pminsd %xmm8, %xmm9", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pminub, RegMem::reg(xmm3), w_xmm2, None), + Inst::xmm_rm_r(SseOpcode::Pminub, RegMem::reg(xmm3), w_xmm2), "660FDAD3", "pminub %xmm3, %xmm2", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pminuw, RegMem::reg(xmm3), w_xmm2, None), + Inst::xmm_rm_r(SseOpcode::Pminuw, RegMem::reg(xmm3), w_xmm2), "660F383AD3", "pminuw %xmm3, %xmm2", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pminud, RegMem::reg(xmm3), w_xmm2, None), + Inst::xmm_rm_r(SseOpcode::Pminud, RegMem::reg(xmm3), w_xmm2), "660F383BD3", "pminud %xmm3, %xmm2", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::reg(xmm11), w_xmm2, None), + Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::reg(xmm11), w_xmm2), "66410FEFD3", "pxor %xmm11, %xmm2", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::reg(xmm11), w_xmm2, None), + Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::reg(xmm11), w_xmm2), "66410F3800D3", "pshufb %xmm11, %xmm2", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Packsswb, RegMem::reg(xmm11), w_xmm2, None), + Inst::xmm_rm_r(SseOpcode::Packsswb, RegMem::reg(xmm11), w_xmm2), "66410F63D3", "packsswb %xmm11, %xmm2", )); @@ -3301,25 +3160,25 @@ fn test_x64_emit() { // ======================================================== // XMM_RM_R: Integer Conversion insns.push(( - Inst::xmm_rm_r(SseOpcode::Cvtdq2ps, RegMem::reg(xmm1), w_xmm8, None), + Inst::xmm_rm_r(SseOpcode::Cvtdq2ps, RegMem::reg(xmm1), w_xmm8), "440F5BC1", "cvtdq2ps %xmm1, %xmm8", )); insns.push(( - Inst::xmm_rm_r(SseOpcode::Cvttps2dq, RegMem::reg(xmm9), w_xmm8, None), + Inst::xmm_rm_r(SseOpcode::Cvttps2dq, RegMem::reg(xmm9), w_xmm8), "F3450F5BC1", "cvttps2dq %xmm9, %xmm8", )); // XMM_Mov_R_M: float stores insns.push(( - Inst::xmm_mov_r_m(SseOpcode::Movss, xmm15, Amode::imm_reg(128, r12), None), + Inst::xmm_mov_r_m(SseOpcode::Movss, xmm15, Amode::imm_reg(128, r12)), "F3450F11BC2480000000", "movss %xmm15, 128(%r12)", )); insns.push(( - Inst::xmm_mov_r_m(SseOpcode::Movsd, xmm1, Amode::imm_reg(0, rsi), None), + Inst::xmm_mov_r_m(SseOpcode::Movsd, xmm1, Amode::imm_reg(0, rsi)), "F20F110E", "movsd %xmm1, 0(%rsi)", )); @@ -3526,12 +3385,12 @@ fn test_x64_emit() { // ======================================================== // XmmRmRImm insns.push(( - Inst::xmm_rm_r_imm(SseOpcode::Cmppd, RegMem::reg(xmm5), w_xmm1, 2, false, None), + Inst::xmm_rm_r_imm(SseOpcode::Cmppd, RegMem::reg(xmm5), w_xmm1, 2, false), "660FC2CD02", "cmppd $2, %xmm5, %xmm1", )); insns.push(( - Inst::xmm_rm_r_imm(SseOpcode::Cmpps, RegMem::reg(xmm15), w_xmm7, 0, false, None), + Inst::xmm_rm_r_imm(SseOpcode::Cmpps, RegMem::reg(xmm15), w_xmm7, 0, false), "410FC2FF00", "cmpps $0, %xmm15, %xmm7", )); @@ -3549,7 +3408,6 @@ fn test_x64_emit() { ty: types::I8, src: rbx, dst: am1, - srcloc: None, }, "F0410FB09C9241010000", "lock cmpxchgb %bl, 321(%r10,%rdx,4)", @@ -3560,7 +3418,6 @@ fn test_x64_emit() { ty: types::I8, src: rdx, dst: am2.clone(), - srcloc: None, }, "F00FB094F1C7CFFFFF", "lock cmpxchgb %dl, -12345(%rcx,%rsi,8)", @@ -3570,7 +3427,6 @@ fn test_x64_emit() { ty: types::I8, src: rsi, dst: am2.clone(), - srcloc: None, }, "F0400FB0B4F1C7CFFFFF", "lock cmpxchgb %sil, -12345(%rcx,%rsi,8)", @@ -3580,7 +3436,6 @@ fn test_x64_emit() { ty: types::I8, src: r10, dst: am2.clone(), - srcloc: None, }, "F0440FB094F1C7CFFFFF", "lock cmpxchgb %r10b, -12345(%rcx,%rsi,8)", @@ -3590,7 +3445,6 @@ fn test_x64_emit() { ty: types::I8, src: r15, dst: am2.clone(), - srcloc: None, }, "F0440FB0BCF1C7CFFFFF", "lock cmpxchgb %r15b, -12345(%rcx,%rsi,8)", @@ -3601,7 +3455,6 @@ fn test_x64_emit() { ty: types::I16, src: rsi, dst: am2.clone(), - srcloc: None, }, "66F00FB1B4F1C7CFFFFF", "lock cmpxchgw %si, -12345(%rcx,%rsi,8)", @@ -3611,7 +3464,6 @@ fn test_x64_emit() { ty: types::I16, src: r10, dst: am2.clone(), - srcloc: None, }, "66F0440FB194F1C7CFFFFF", "lock cmpxchgw %r10w, -12345(%rcx,%rsi,8)", @@ -3622,7 +3474,6 @@ fn test_x64_emit() { ty: types::I32, src: rsi, dst: am2.clone(), - srcloc: None, }, "F00FB1B4F1C7CFFFFF", "lock cmpxchgl %esi, -12345(%rcx,%rsi,8)", @@ -3632,7 +3483,6 @@ fn test_x64_emit() { ty: types::I32, src: r10, dst: am2.clone(), - srcloc: None, }, "F0440FB194F1C7CFFFFF", "lock cmpxchgl %r10d, -12345(%rcx,%rsi,8)", @@ -3643,7 +3493,6 @@ fn test_x64_emit() { ty: types::I64, src: rsi, dst: am2.clone(), - srcloc: None, }, "F0480FB1B4F1C7CFFFFF", "lock cmpxchgq %rsi, -12345(%rcx,%rsi,8)", @@ -3653,7 +3502,6 @@ fn test_x64_emit() { ty: types::I64, src: r10, dst: am2.clone(), - srcloc: None, }, "F04C0FB194F1C7CFFFFF", "lock cmpxchgq %r10, -12345(%rcx,%rsi,8)", @@ -3661,22 +3509,22 @@ fn test_x64_emit() { // AtomicRmwSeq insns.push(( - Inst::AtomicRmwSeq { ty: types::I8, op: inst_common::AtomicRmwOp::Or, srcloc: None }, + Inst::AtomicRmwSeq { ty: types::I8, op: inst_common::AtomicRmwOp::Or, }, "490FB6014989C34D09D3F0450FB0190F85EFFFFFFF", "atomically { 8_bits_at_[%r9]) Or= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }" )); insns.push(( - Inst::AtomicRmwSeq { ty: types::I16, op: inst_common::AtomicRmwOp::And, srcloc: None }, + Inst::AtomicRmwSeq { ty: types::I16, op: inst_common::AtomicRmwOp::And, }, "490FB7014989C34D21D366F0450FB1190F85EEFFFFFF", "atomically { 16_bits_at_[%r9]) And= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }" )); insns.push(( - Inst::AtomicRmwSeq { ty: types::I32, op: inst_common::AtomicRmwOp::Xchg, srcloc: None }, + Inst::AtomicRmwSeq { ty: types::I32, op: inst_common::AtomicRmwOp::Xchg, }, "418B014989C34D89D3F0450FB1190F85EFFFFFFF", "atomically { 32_bits_at_[%r9]) Xchg= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }" )); insns.push(( - Inst::AtomicRmwSeq { ty: types::I64, op: inst_common::AtomicRmwOp::Add, srcloc: None }, + Inst::AtomicRmwSeq { ty: types::I64, op: inst_common::AtomicRmwOp::Add, }, "498B014989C34D01D3F04D0FB1190F85EFFFFFFF", "atomically { 64_bits_at_[%r9]) Add= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }" )); @@ -3709,8 +3557,8 @@ fn test_x64_emit() { insns.push((Inst::Hlt, "CC", "hlt")); - let trap_info = (SourceLoc::default(), TrapCode::UnreachableCodeReached); - insns.push((Inst::Ud2 { trap_info }, "0F0B", "ud2 unreachable")); + let trap_code = TrapCode::UnreachableCodeReached; + insns.push((Inst::Ud2 { trap_code }, "0F0B", "ud2 unreachable")); // ======================================================== // Actually run the tests! diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 08680166e8..1172b22eff 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -71,7 +71,6 @@ pub enum Inst { size: u8, // 1, 2, 4 or 8 signed: bool, divisor: RegMem, - loc: SourceLoc, }, /// The high bits (RDX) of a (un)signed multiply: RDX:RAX := RAX * rhs. @@ -95,7 +94,6 @@ pub enum Inst { /// different from the temporary. divisor: Writable, tmp: Option>, - loc: SourceLoc, }, /// Do a sign-extend based on the sign of the value in rax into rdx: (cwd cdq cqo) @@ -126,16 +124,12 @@ pub enum Inst { ext_mode: ExtMode, src: RegMem, dst: Writable, - /// Source location, if the memory access can be out-of-bounds. - srcloc: Option, }, /// A plain 64-bit integer load, since MovZX_RM_R can't represent that. Mov64MR { src: SyntheticAmode, dst: Writable, - /// Source location, if the memory access can be out-of-bounds. - srcloc: Option, }, /// Loads the memory address of addr into dst. @@ -149,8 +143,6 @@ pub enum Inst { ext_mode: ExtMode, src: RegMem, dst: Writable, - /// Source location, if the memory access can be out-of-bounds. - srcloc: Option, }, /// Integer stores: mov (b w l q) reg addr. @@ -158,8 +150,6 @@ pub enum Inst { size: u8, // 1, 2, 4 or 8. src: Reg, dst: SyntheticAmode, - /// Source location, if the memory access can be out-of-bounds. - srcloc: Option, }, /// Arithmetic shifts: (shl shr sar) (b w l q) imm reg. @@ -213,7 +203,6 @@ pub enum Inst { op: SseOpcode, src: RegMem, dst: Writable, - srcloc: Option, }, /// XMM (scalar or vector) unary op: mov between XMM registers (32 64) (reg addr) reg, sqrt, @@ -226,8 +215,6 @@ pub enum Inst { op: SseOpcode, src: RegMem, dst: Writable, - /// Source location, if the memory access can be out-of-bounds. - srcloc: Option, }, /// XMM (scalar or vector) unary op (from xmm to reg/mem): stores, movd, movq @@ -235,8 +222,6 @@ pub enum Inst { op: SseOpcode, src: Reg, dst: SyntheticAmode, - /// Source location, if the memory access can be out-of-bounds. - srcloc: Option, }, /// XMM (vector) unary op (to move a constant value into an xmm register): movups @@ -289,7 +274,6 @@ pub enum Inst { dst: Writable, tmp_gpr: Writable, tmp_xmm: Writable, - srcloc: SourceLoc, }, /// Converts a scalar xmm to an unsigned int32/int64. @@ -305,7 +289,6 @@ pub enum Inst { dst: Writable, tmp_gpr: Writable, tmp_xmm: Writable, - srcloc: SourceLoc, }, /// A sequence to compute min/max with the proper NaN semantics for xmm registers. @@ -340,7 +323,6 @@ pub enum Inst { dst: Writable, imm: u8, is64: bool, - srcloc: Option, }, // ===================================== @@ -350,7 +332,6 @@ pub enum Inst { dest: ExternalName, uses: Vec, defs: Vec>, - loc: SourceLoc, opcode: Opcode, }, @@ -359,7 +340,6 @@ pub enum Inst { dest: RegMem, uses: Vec, defs: Vec>, - loc: SourceLoc, opcode: Opcode, }, @@ -408,23 +388,18 @@ pub enum Inst { JmpUnknown { target: RegMem }, /// Traps if the condition code is set. - TrapIf { - cc: CC, - trap_code: TrapCode, - srcloc: SourceLoc, - }, + TrapIf { cc: CC, trap_code: TrapCode }, /// A debug trap. Hlt, /// An instruction that will always trigger the illegal instruction exception. - Ud2 { trap_info: (SourceLoc, TrapCode) }, + Ud2 { trap_code: TrapCode }, /// Loads an external symbol in a register, with a relocation: movabsq $name, dst LoadExtName { dst: Writable, name: Box, - srcloc: SourceLoc, offset: i64, }, @@ -443,7 +418,6 @@ pub enum Inst { ty: Type, // I8, I16, I32 or I64 src: Reg, dst: SyntheticAmode, - srcloc: Option, }, /// A synthetic instruction, based on a loop around a native `lock cmpxchg` instruction. @@ -472,7 +446,6 @@ pub enum Inst { AtomicRmwSeq { ty: Type, // I8, I16, I32 or I64 op: inst_common::AtomicRmwOp, - srcloc: Option, }, /// A memory fence (mfence, lfence or sfence). @@ -617,14 +590,13 @@ impl Inst { Inst::Neg { size, src } } - pub(crate) fn div(size: u8, signed: bool, divisor: RegMem, loc: SourceLoc) -> Inst { + pub(crate) fn div(size: u8, signed: bool, divisor: RegMem) -> Inst { divisor.assert_regclass_is(RegClass::I64); debug_assert!(size == 8 || size == 4 || size == 2 || size == 1); Inst::Div { size, signed, divisor, - loc, } } @@ -639,7 +611,6 @@ impl Inst { size: u8, divisor: Writable, tmp: Option>, - loc: SourceLoc, ) -> Inst { debug_assert!(size == 8 || size == 4 || size == 2 || size == 1); debug_assert!(divisor.to_reg().get_class() == RegClass::I64); @@ -651,7 +622,6 @@ impl Inst { size, divisor, tmp, - loc, } } @@ -679,20 +649,10 @@ impl Inst { } // TODO Can be replaced by `Inst::move` (high-level) and `Inst::unary_rm_r` (low-level) - pub(crate) fn xmm_mov( - op: SseOpcode, - src: RegMem, - dst: Writable, - srcloc: Option, - ) -> Inst { + pub(crate) fn xmm_mov(op: SseOpcode, src: RegMem, dst: Writable) -> Inst { src.assert_regclass_is(RegClass::V128); debug_assert!(dst.to_reg().get_class() == RegClass::V128); - Inst::XmmUnaryRmR { - op, - src, - dst, - srcloc, - } + Inst::XmmUnaryRmR { op, src, dst } } pub(crate) fn xmm_load_const(src: VCodeConstant, dst: Writable, ty: Type) -> Inst { @@ -705,28 +665,13 @@ impl Inst { pub(crate) fn xmm_unary_rm_r(op: SseOpcode, src: RegMem, dst: Writable) -> Inst { src.assert_regclass_is(RegClass::V128); debug_assert!(dst.to_reg().get_class() == RegClass::V128); - Inst::XmmUnaryRmR { - op, - src, - dst, - srcloc: None, - } + Inst::XmmUnaryRmR { op, src, dst } } - pub(crate) fn xmm_rm_r( - op: SseOpcode, - src: RegMem, - dst: Writable, - srcloc: Option, - ) -> Self { + pub(crate) fn xmm_rm_r(op: SseOpcode, src: RegMem, dst: Writable) -> Self { src.assert_regclass_is(RegClass::V128); debug_assert!(dst.to_reg().get_class() == RegClass::V128); - Inst::XmmRmR { - op, - src, - dst, - srcloc, - } + Inst::XmmRmR { op, src, dst } } pub(crate) fn xmm_uninit_value(dst: Writable) -> Self { @@ -734,18 +679,12 @@ impl Inst { Inst::XmmUninitializedValue { dst } } - pub(crate) fn xmm_mov_r_m( - op: SseOpcode, - src: Reg, - dst: impl Into, - srcloc: Option, - ) -> Inst { + pub(crate) fn xmm_mov_r_m(op: SseOpcode, src: Reg, dst: impl Into) -> Inst { debug_assert!(src.get_class() == RegClass::V128); Inst::XmmMovRM { op, src, dst: dst.into(), - srcloc, } } @@ -815,7 +754,6 @@ impl Inst { dst: Writable, tmp_gpr: Writable, tmp_xmm: Writable, - srcloc: SourceLoc, ) -> Inst { debug_assert!(src.to_reg().get_class() == RegClass::V128); debug_assert!(tmp_xmm.to_reg().get_class() == RegClass::V128); @@ -829,7 +767,6 @@ impl Inst { dst, tmp_gpr, tmp_xmm, - srcloc, } } @@ -841,7 +778,6 @@ impl Inst { dst: Writable, tmp_gpr: Writable, tmp_xmm: Writable, - srcloc: SourceLoc, ) -> Inst { debug_assert!(src.to_reg().get_class() == RegClass::V128); debug_assert!(tmp_xmm.to_reg().get_class() == RegClass::V128); @@ -855,7 +791,6 @@ impl Inst { dst, tmp_gpr, tmp_xmm, - srcloc, } } @@ -881,7 +816,6 @@ impl Inst { dst: Writable, imm: u8, is64: bool, - srcloc: Option, ) -> Inst { Inst::XmmRmRImm { op, @@ -889,24 +823,13 @@ impl Inst { dst, imm, is64, - srcloc, } } - pub(crate) fn movzx_rm_r( - ext_mode: ExtMode, - src: RegMem, - dst: Writable, - srcloc: Option, - ) -> Inst { + pub(crate) fn movzx_rm_r(ext_mode: ExtMode, src: RegMem, dst: Writable) -> Inst { src.assert_regclass_is(RegClass::I64); debug_assert!(dst.to_reg().get_class() == RegClass::I64); - Inst::MovzxRmR { - ext_mode, - src, - dst, - srcloc, - } + Inst::MovzxRmR { ext_mode, src, dst } } pub(crate) fn xmm_rmi_reg(opcode: SseOpcode, src: RegMemImm, dst: Writable) -> Inst { @@ -915,41 +838,26 @@ impl Inst { Inst::XmmRmiReg { opcode, src, dst } } - pub(crate) fn movsx_rm_r( - ext_mode: ExtMode, - src: RegMem, - dst: Writable, - srcloc: Option, - ) -> Inst { + pub(crate) fn movsx_rm_r(ext_mode: ExtMode, src: RegMem, dst: Writable) -> Inst { src.assert_regclass_is(RegClass::I64); debug_assert!(dst.to_reg().get_class() == RegClass::I64); - Inst::MovsxRmR { - ext_mode, - src, - dst, - srcloc, - } + Inst::MovsxRmR { ext_mode, src, dst } } - pub(crate) fn mov64_m_r( - src: impl Into, - dst: Writable, - srcloc: Option, - ) -> Inst { + pub(crate) fn mov64_m_r(src: impl Into, dst: Writable) -> Inst { debug_assert!(dst.to_reg().get_class() == RegClass::I64); Inst::Mov64MR { src: src.into(), dst, - srcloc, } } /// A convenience function to be able to use a RegMem as the source of a move. - pub(crate) fn mov64_rm_r(src: RegMem, dst: Writable, srcloc: Option) -> Inst { + pub(crate) fn mov64_rm_r(src: RegMem, dst: Writable) -> Inst { src.assert_regclass_is(RegClass::I64); match src { RegMem::Reg { reg } => Self::mov_r_r(true, reg, dst), - RegMem::Mem { addr } => Self::mov64_m_r(addr, dst, srcloc), + RegMem::Mem { addr } => Self::mov64_m_r(addr, dst), } } @@ -957,7 +865,6 @@ impl Inst { size: u8, // 1, 2, 4 or 8 src: Reg, dst: impl Into, - srcloc: Option, ) -> Inst { debug_assert!(size == 8 || size == 4 || size == 2 || size == 1); debug_assert!(src.get_class() == RegClass::I64); @@ -965,7 +872,6 @@ impl Inst { size, src, dst: dst.into(), - srcloc, } } @@ -1011,9 +917,9 @@ impl Inst { Inst::CmpRmiR { size, src, dst } } - pub(crate) fn trap(srcloc: SourceLoc, trap_code: TrapCode) -> Inst { + pub(crate) fn trap(trap_code: TrapCode) -> Inst { Inst::Ud2 { - trap_info: (srcloc, trap_code), + trap_code: trap_code, } } @@ -1053,14 +959,12 @@ impl Inst { dest: ExternalName, uses: Vec, defs: Vec>, - loc: SourceLoc, opcode: Opcode, ) -> Inst { Inst::CallKnown { dest, uses, defs, - loc, opcode, } } @@ -1069,7 +973,6 @@ impl Inst { dest: RegMem, uses: Vec, defs: Vec>, - loc: SourceLoc, opcode: Opcode, ) -> Inst { dest.assert_regclass_is(RegClass::I64); @@ -1077,7 +980,6 @@ impl Inst { dest, uses, defs, - loc, opcode, } } @@ -1111,12 +1013,8 @@ impl Inst { Inst::JmpUnknown { target } } - pub(crate) fn trap_if(cc: CC, trap_code: TrapCode, srcloc: SourceLoc) -> Inst { - Inst::TrapIf { - cc, - trap_code, - srcloc, - } + pub(crate) fn trap_if(cc: CC, trap_code: TrapCode) -> Inst { + Inst::TrapIf { cc, trap_code } } /// Choose which instruction to use for loading a register value from memory. For loads smaller @@ -1127,7 +1025,6 @@ impl Inst { from_addr: impl Into, to_reg: Writable, ext_kind: ExtKind, - srcloc: Option, ) -> Inst { let rc = to_reg.to_reg().get_class(); match rc { @@ -1143,10 +1040,10 @@ impl Inst { // Values smaller than 64 bits must be extended in some way. match ext_kind { ExtKind::SignExtend => { - Inst::movsx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg, srcloc) + Inst::movsx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg) } ExtKind::ZeroExtend => { - Inst::movzx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg, srcloc) + Inst::movzx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg) } ExtKind::None => panic!( "expected an extension kind for extension mode: {:?}", @@ -1155,7 +1052,7 @@ impl Inst { } } else { // 64-bit values can be moved directly. - Inst::mov64_m_r(from_addr, to_reg, srcloc) + Inst::mov64_m_r(from_addr, to_reg) } } RegClass::V128 => { @@ -1174,18 +1071,13 @@ impl Inst { } /// Choose which instruction to use for storing a register value to memory. - pub(crate) fn store( - ty: Type, - from_reg: Reg, - to_addr: impl Into, - srcloc: Option, - ) -> Inst { + pub(crate) fn store(ty: Type, from_reg: Reg, to_addr: impl Into) -> Inst { let rc = from_reg.get_class(); match rc { RegClass::I64 => { // Always store the full register, to ensure that the high bits are properly set // when doing a full reload. - Inst::mov_r_m(8 /* bytes */, from_reg, to_addr, srcloc) + Inst::mov_r_m(8 /* bytes */, from_reg, to_addr) } RegClass::V128 => { let opcode = match ty { @@ -1196,7 +1088,7 @@ impl Inst { _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqu, _ => unimplemented!("unable to store type: {}", ty), }; - Inst::xmm_mov_r_m(opcode, from_reg, to_addr, srcloc) + Inst::xmm_mov_r_m(opcode, from_reg, to_addr) } _ => panic!("unable to generate store for register class: {:?}", rc), } @@ -1247,26 +1139,16 @@ impl Inst { /// Choose which instruction to use for comparing two values for equality. pub(crate) fn equals(ty: Type, from: RegMem, to: Writable) -> Inst { match ty { - types::I8X16 | types::B8X16 => Inst::xmm_rm_r(SseOpcode::Pcmpeqb, from, to, None), - types::I16X8 | types::B16X8 => Inst::xmm_rm_r(SseOpcode::Pcmpeqw, from, to, None), - types::I32X4 | types::B32X4 => Inst::xmm_rm_r(SseOpcode::Pcmpeqd, from, to, None), - types::I64X2 | types::B64X2 => Inst::xmm_rm_r(SseOpcode::Pcmpeqq, from, to, None), - types::F32X4 => Inst::xmm_rm_r_imm( - SseOpcode::Cmpps, - from, - to, - FcmpImm::Equal.encode(), - false, - None, - ), - types::F64X2 => Inst::xmm_rm_r_imm( - SseOpcode::Cmppd, - from, - to, - FcmpImm::Equal.encode(), - false, - None, - ), + types::I8X16 | types::B8X16 => Inst::xmm_rm_r(SseOpcode::Pcmpeqb, from, to), + types::I16X8 | types::B16X8 => Inst::xmm_rm_r(SseOpcode::Pcmpeqw, from, to), + types::I32X4 | types::B32X4 => Inst::xmm_rm_r(SseOpcode::Pcmpeqd, from, to), + types::I64X2 | types::B64X2 => Inst::xmm_rm_r(SseOpcode::Pcmpeqq, from, to), + types::F32X4 => { + Inst::xmm_rm_r_imm(SseOpcode::Cmpps, from, to, FcmpImm::Equal.encode(), false) + } + types::F64X2 => { + Inst::xmm_rm_r_imm(SseOpcode::Cmppd, from, to, FcmpImm::Equal.encode(), false) + } _ => unimplemented!("unimplemented type for Inst::equals: {}", ty), } } @@ -1274,11 +1156,9 @@ impl Inst { /// Choose which instruction to use for computing a bitwise AND on two values. pub(crate) fn and(ty: Type, from: RegMem, to: Writable) -> Inst { match ty { - types::F32X4 => Inst::xmm_rm_r(SseOpcode::Andps, from, to, None), - types::F64X2 => Inst::xmm_rm_r(SseOpcode::Andpd, from, to, None), - _ if ty.is_vector() && ty.bits() == 128 => { - Inst::xmm_rm_r(SseOpcode::Pand, from, to, None) - } + types::F32X4 => Inst::xmm_rm_r(SseOpcode::Andps, from, to), + types::F64X2 => Inst::xmm_rm_r(SseOpcode::Andpd, from, to), + _ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Pand, from, to), _ => unimplemented!("unimplemented type for Inst::and: {}", ty), } } @@ -1286,11 +1166,9 @@ impl Inst { /// Choose which instruction to use for computing a bitwise AND NOT on two values. pub(crate) fn and_not(ty: Type, from: RegMem, to: Writable) -> Inst { match ty { - types::F32X4 => Inst::xmm_rm_r(SseOpcode::Andnps, from, to, None), - types::F64X2 => Inst::xmm_rm_r(SseOpcode::Andnpd, from, to, None), - _ if ty.is_vector() && ty.bits() == 128 => { - Inst::xmm_rm_r(SseOpcode::Pandn, from, to, None) - } + types::F32X4 => Inst::xmm_rm_r(SseOpcode::Andnps, from, to), + types::F64X2 => Inst::xmm_rm_r(SseOpcode::Andnpd, from, to), + _ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Pandn, from, to), _ => unimplemented!("unimplemented type for Inst::and_not: {}", ty), } } @@ -1298,11 +1176,9 @@ impl Inst { /// Choose which instruction to use for computing a bitwise OR on two values. pub(crate) fn or(ty: Type, from: RegMem, to: Writable) -> Inst { match ty { - types::F32X4 => Inst::xmm_rm_r(SseOpcode::Orps, from, to, None), - types::F64X2 => Inst::xmm_rm_r(SseOpcode::Orpd, from, to, None), - _ if ty.is_vector() && ty.bits() == 128 => { - Inst::xmm_rm_r(SseOpcode::Por, from, to, None) - } + types::F32X4 => Inst::xmm_rm_r(SseOpcode::Orps, from, to), + types::F64X2 => Inst::xmm_rm_r(SseOpcode::Orpd, from, to), + _ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Por, from, to), _ => unimplemented!("unimplemented type for Inst::or: {}", ty), } } @@ -1310,11 +1186,9 @@ impl Inst { /// Choose which instruction to use for computing a bitwise XOR on two values. pub(crate) fn xor(ty: Type, from: RegMem, to: Writable) -> Inst { match ty { - types::F32X4 => Inst::xmm_rm_r(SseOpcode::Xorps, from, to, None), - types::F64X2 => Inst::xmm_rm_r(SseOpcode::Xorpd, from, to, None), - _ if ty.is_vector() && ty.bits() == 128 => { - Inst::xmm_rm_r(SseOpcode::Pxor, from, to, None) - } + types::F32X4 => Inst::xmm_rm_r(SseOpcode::Xorps, from, to), + types::F64X2 => Inst::xmm_rm_r(SseOpcode::Xorpd, from, to), + _ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Pxor, from, to), _ => unimplemented!("unimplemented type for Inst::xor: {}", ty), } } @@ -1839,7 +1713,7 @@ impl PrettyPrint for Inst { Inst::Hlt => "hlt".into(), - Inst::Ud2 { trap_info } => format!("ud2 {}", trap_info.1), + Inst::Ud2 { trap_code } => format!("ud2 {}", trap_code), } } } @@ -2627,7 +2501,6 @@ impl MachInst for Inst { SseOpcode::Xorps, RegMem::reg(to_reg.to_reg()), to_reg, - None, )); } else { let tmp = alloc_tmp(RegClass::I64, types::I32); @@ -2646,7 +2519,6 @@ impl MachInst for Inst { SseOpcode::Xorpd, RegMem::reg(to_reg.to_reg()), to_reg, - None, )); } else { let tmp = alloc_tmp(RegClass::I64, types::I64); @@ -2717,6 +2589,8 @@ pub struct EmitState { pub(crate) nominal_sp_to_fp: i64, /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`. stack_map: Option, + /// Current source location. + cur_srcloc: SourceLoc, } /// Constant state used during emissions of a sequence of instructions. @@ -2757,12 +2631,17 @@ impl MachInstEmitState for EmitState { virtual_sp_offset: 0, nominal_sp_to_fp: abi.frame_size() as i64, stack_map: None, + cur_srcloc: SourceLoc::default(), } } fn pre_safepoint(&mut self, stack_map: StackMap) { self.stack_map = Some(stack_map); } + + fn pre_sourceloc(&mut self, srcloc: SourceLoc) { + self.cur_srcloc = srcloc; + } } impl EmitState { @@ -2773,6 +2652,10 @@ impl EmitState { fn clear_post_insn(&mut self) { self.stack_map = None; } + + fn cur_srcloc(&self) -> SourceLoc { + self.cur_srcloc + } } /// A label-use (internal relocation) in generated code. diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index 7e1c2d51ab..8564a84e63 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -3,7 +3,7 @@ use crate::data_value::DataValue; use crate::ir::{ condcodes::FloatCC, condcodes::IntCC, types, AbiParam, ArgumentPurpose, ExternalName, - Inst as IRInst, InstructionData, LibCall, Opcode, Signature, SourceLoc, Type, + Inst as IRInst, InstructionData, LibCall, Opcode, Signature, Type, }; use crate::isa::x64::abi::*; use crate::isa::x64::inst::args::*; @@ -156,14 +156,10 @@ fn extend_input_to_reg(ctx: Ctx, spec: InsnInput, ext_spec: ExtSpec) -> Reg { let dst = ctx.alloc_tmp(RegClass::I64, requested_ty); match ext_spec { ExtSpec::ZeroExtendTo32 | ExtSpec::ZeroExtendTo64 => { - ctx.emit(Inst::movzx_rm_r( - ext_mode, src, dst, /* infallible */ None, - )) + ctx.emit(Inst::movzx_rm_r(ext_mode, src, dst)) } ExtSpec::SignExtendTo32 | ExtSpec::SignExtendTo64 => { - ctx.emit(Inst::movsx_rm_r( - ext_mode, src, dst, /* infallible */ None, - )) + ctx.emit(Inst::movsx_rm_r(ext_mode, src, dst)) } } dst.to_reg() @@ -227,7 +223,6 @@ fn emit_insert_lane>( dst: Writable, lane: u8, ty: Type, - srcloc: Option, ) { if !ty.is_float() { let (sse_op, is64) = match ty.lane_bits() { @@ -237,13 +232,13 @@ fn emit_insert_lane>( 64 => (SseOpcode::Pinsrd, true), _ => panic!("Unable to insertlane for lane size: {}", ty.lane_bits()), }; - ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, lane, is64, srcloc)); + ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, lane, is64)); } else if ty == types::F32 { let sse_op = SseOpcode::Insertps; // Insert 32-bits from replacement (at index 00, bits 7:8) to vector (lane // shifted into bits 5:6). let lane = 0b00_00_00_00 | lane << 4; - ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, lane, false, srcloc)); + ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, lane, false)); } else if ty == types::F64 { let sse_op = match lane { // Move the lowest quadword in replacement to vector without changing @@ -257,7 +252,7 @@ fn emit_insert_lane>( // Here we use the `xmm_rm_r` encoding because it correctly tells the register // allocator how we are using `dst`: we are using `dst` as a `mod` whereas other // encoding formats like `xmm_unary_rm_r` treat it as a `def`. - ctx.emit(Inst::xmm_rm_r(sse_op, src, dst, srcloc)); + ctx.emit(Inst::xmm_rm_r(sse_op, src, dst)); } else { panic!("unable to emit insertlane for type: {}", ty) } @@ -407,8 +402,7 @@ fn emit_vm_call>( let sig = make_libcall_sig(ctx, insn, call_conv, types::I64); let caller_conv = ctx.abi().call_conv(); - let loc = ctx.srcloc(insn); - let mut abi = X64ABICaller::from_func(&sig, &extname, dist, loc, caller_conv)?; + let mut abi = X64ABICaller::from_func(&sig, &extname, dist, caller_conv)?; abi.emit_stack_pre_adjust(ctx); @@ -695,7 +689,6 @@ fn lower_insn_to_regs>( SseOpcode::Pmuludq, RegMem::reg(lhs.clone()), rhs_1, - None, )); // B' = B @@ -709,12 +702,7 @@ fn lower_insn_to_regs>( RegMemImm::imm(32), lhs_1, )); - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pmuludq, - RegMem::reg(rhs), - lhs_1, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmuludq, RegMem::reg(rhs), lhs_1)); // B' = B' + A' // B' = B' << 32 @@ -722,7 +710,6 @@ fn lower_insn_to_regs>( SseOpcode::Paddq, RegMem::reg(rhs_1.to_reg()), lhs_1, - None, )); ctx.emit(Inst::xmm_rmi_reg( SseOpcode::Psllq, @@ -739,13 +726,11 @@ fn lower_insn_to_regs>( SseOpcode::Pmuludq, RegMem::reg(lhs.clone()), rhs_1, - None, )); ctx.emit(Inst::xmm_rm_r( SseOpcode::Paddq, RegMem::reg(lhs_1.to_reg()), rhs_1, - None, )); ctx.emit(Inst::gen_move(dst, rhs_1.to_reg(), ty)); return Ok(()); @@ -780,7 +765,7 @@ fn lower_insn_to_regs>( // Move the `lhs` to the same register as `dst`. ctx.emit(Inst::gen_move(dst, lhs, ty)); - ctx.emit(Inst::xmm_rm_r(sse_op, rhs, dst, None)); + ctx.emit(Inst::xmm_rm_r(sse_op, rhs, dst)); } else { let is_64 = ty == types::I64; let alu_op = match op { @@ -838,7 +823,7 @@ fn lower_insn_to_regs>( // Note the flipping of operands: the `rhs` operand is used as the destination instead // of the `lhs` as in the other bit operations above (e.g. `band`). ctx.emit(Inst::gen_move(dst, rhs, ty)); - ctx.emit(Inst::xmm_rm_r(sse_op, lhs, dst, None)); + ctx.emit(Inst::xmm_rm_r(sse_op, lhs, dst)); } Opcode::Iabs => { @@ -894,7 +879,7 @@ fn lower_insn_to_regs>( // Move the `lhs` to the same register as `dst`. ctx.emit(Inst::gen_move(dst, lhs, ty)); - ctx.emit(Inst::xmm_rm_r(sse_op, rhs, dst, None)); + ctx.emit(Inst::xmm_rm_r(sse_op, rhs, dst)); } else { panic!("Unsupported type for {} instruction: {}", op, ty); } @@ -1017,9 +1002,8 @@ fn lower_insn_to_regs>( SseOpcode::Pxor, RegMem::reg(tmp.to_reg()), tmp, - None, )); - ctx.emit(Inst::xmm_rm_r(subtract_opcode, src, tmp, None)); + ctx.emit(Inst::xmm_rm_r(subtract_opcode, src, tmp)); ctx.emit(Inst::xmm_unary_rm_r( SseOpcode::Movapd, RegMem::reg(tmp.to_reg()), @@ -1147,7 +1131,7 @@ fn lower_insn_to_regs>( let cst = ctx.alloc_tmp(RegClass::I64, types::I64); // mov src, tmp1 - ctx.emit(Inst::mov64_rm_r(src.clone(), tmp1, None)); + ctx.emit(Inst::mov64_rm_r(src.clone(), tmp1)); // shr $1, tmp1 ctx.emit(Inst::shift_r( @@ -1169,7 +1153,7 @@ fn lower_insn_to_regs>( )); // mov src, tmp2 - ctx.emit(Inst::mov64_rm_r(src, tmp2, None)); + ctx.emit(Inst::mov64_rm_r(src, tmp2)); // sub tmp1, tmp2 ctx.emit(Inst::alu_rmi_r( @@ -1228,7 +1212,7 @@ fn lower_insn_to_regs>( )); // mov tmp2, dst - ctx.emit(Inst::mov64_rm_r(RegMem::reg(tmp2.to_reg()), dst, None)); + ctx.emit(Inst::mov64_rm_r(RegMem::reg(tmp2.to_reg()), dst)); // shr $4, dst ctx.emit(Inst::shift_r(8, ShiftKind::ShiftRightLogical, Some(4), dst)); @@ -1278,7 +1262,7 @@ fn lower_insn_to_regs>( let tmp2 = ctx.alloc_tmp(RegClass::I64, types::I64); // mov src, tmp1 - ctx.emit(Inst::mov64_rm_r(src.clone(), tmp1, None)); + ctx.emit(Inst::mov64_rm_r(src.clone(), tmp1)); // shr $1, tmp1 ctx.emit(Inst::shift_r( @@ -1297,7 +1281,7 @@ fn lower_insn_to_regs>( )); // mov src, tmp2 - ctx.emit(Inst::mov64_rm_r(src, tmp2, None)); + ctx.emit(Inst::mov64_rm_r(src, tmp2)); // sub tmp1, tmp2 ctx.emit(Inst::alu_rmi_r( @@ -1356,7 +1340,7 @@ fn lower_insn_to_regs>( )); // mov tmp2, dst - ctx.emit(Inst::mov64_rm_r(RegMem::reg(tmp2.to_reg()), dst, None)); + ctx.emit(Inst::mov64_rm_r(RegMem::reg(tmp2.to_reg()), dst)); // shr $4, dst ctx.emit(Inst::shift_r(4, ShiftKind::ShiftRightLogical, Some(4), dst)); @@ -1478,16 +1462,12 @@ fn lower_insn_to_regs>( if let Some(ext_mode) = ext_mode { if op == Opcode::Sextend { - ctx.emit(Inst::movsx_rm_r( - ext_mode, src, dst, /* infallible */ None, - )); + ctx.emit(Inst::movsx_rm_r(ext_mode, src, dst)); } else { - ctx.emit(Inst::movzx_rm_r( - ext_mode, src, dst, /* infallible */ None, - )); + ctx.emit(Inst::movzx_rm_r(ext_mode, src, dst)); } } else { - ctx.emit(Inst::mov64_rm_r(src, dst, /* infallible */ None)); + ctx.emit(Inst::mov64_rm_r(src, dst)); } } @@ -1572,44 +1552,34 @@ fn lower_insn_to_regs>( }; match condcode { - IntCC::Equal => ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst, None)), + IntCC::Equal => ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst)), IntCC::NotEqual => { - ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst, None)); + ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst)); // Emit all 1s into the `tmp` register. let tmp = ctx.alloc_tmp(RegClass::V128, ty); - ctx.emit(Inst::xmm_rm_r(eq(ty), RegMem::from(tmp), tmp, None)); + ctx.emit(Inst::xmm_rm_r(eq(ty), RegMem::from(tmp), tmp)); // Invert the result of the `PCMPEQ*`. - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pxor, - RegMem::from(tmp), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), dst)); } IntCC::SignedGreaterThan | IntCC::SignedLessThan => { - ctx.emit(Inst::xmm_rm_r(gt(ty), input, dst, None)) + ctx.emit(Inst::xmm_rm_r(gt(ty), input, dst)) } IntCC::SignedGreaterThanOrEqual | IntCC::SignedLessThanOrEqual => { - ctx.emit(Inst::xmm_rm_r(mins(ty), input.clone(), dst, None)); - ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst, None)) + ctx.emit(Inst::xmm_rm_r(mins(ty), input.clone(), dst)); + ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst)) } IntCC::UnsignedGreaterThan | IntCC::UnsignedLessThan => { - ctx.emit(Inst::xmm_rm_r(maxu(ty), input.clone(), dst, None)); - ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst, None)); + ctx.emit(Inst::xmm_rm_r(maxu(ty), input.clone(), dst)); + ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst)); // Emit all 1s into the `tmp` register. let tmp = ctx.alloc_tmp(RegClass::V128, ty); - ctx.emit(Inst::xmm_rm_r(eq(ty), RegMem::from(tmp), tmp, None)); + ctx.emit(Inst::xmm_rm_r(eq(ty), RegMem::from(tmp), tmp)); // Invert the result of the `PCMPEQ*`. - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pxor, - RegMem::from(tmp), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), dst)); } IntCC::UnsignedGreaterThanOrEqual | IntCC::UnsignedLessThanOrEqual => { - ctx.emit(Inst::xmm_rm_r(minu(ty), input.clone(), dst, None)); - ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst, None)) + ctx.emit(Inst::xmm_rm_r(minu(ty), input.clone(), dst)); + ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst)) } _ => unimplemented!("Unimplemented comparison code for icmp: {}", condcode), } @@ -1707,7 +1677,7 @@ fn lower_insn_to_regs>( ctx.emit(Inst::gen_move(dst, lhs, input_ty)); // Emit the comparison. - ctx.emit(Inst::xmm_rm_r_imm(op, rhs, dst, imm.encode(), false, None)); + ctx.emit(Inst::xmm_rm_r_imm(op, rhs, dst, imm.encode(), false)); } } @@ -1722,7 +1692,6 @@ fn lower_insn_to_regs>( } Opcode::Call | Opcode::CallIndirect => { - let loc = ctx.srcloc(insn); let caller_conv = ctx.abi().call_conv(); let (mut abi, inputs) = match op { Opcode::Call => { @@ -1731,7 +1700,7 @@ fn lower_insn_to_regs>( assert_eq!(inputs.len(), sig.params.len()); assert_eq!(outputs.len(), sig.returns.len()); ( - X64ABICaller::from_func(sig, &extname, dist, loc, caller_conv)?, + X64ABICaller::from_func(sig, &extname, dist, caller_conv)?, &inputs[..], ) } @@ -1742,7 +1711,7 @@ fn lower_insn_to_regs>( assert_eq!(inputs.len() - 1, sig.params.len()); assert_eq!(outputs.len(), sig.returns.len()); ( - X64ABICaller::from_ptr(sig, ptr, loc, op, caller_conv)?, + X64ABICaller::from_ptr(sig, ptr, op, caller_conv)?, &inputs[1..], ) } @@ -1769,12 +1738,11 @@ fn lower_insn_to_regs>( } Opcode::Trap | Opcode::ResumableTrap => { - let trap_info = (ctx.srcloc(insn), ctx.data(insn).trap_code().unwrap()); - ctx.emit_safepoint(Inst::Ud2 { trap_info }); + let trap_code = ctx.data(insn).trap_code().unwrap(); + ctx.emit_safepoint(Inst::Ud2 { trap_code }); } Opcode::Trapif | Opcode::Trapff => { - let srcloc = ctx.srcloc(insn); let trap_code = ctx.data(insn).trap_code().unwrap(); if matches_input(ctx, inputs[0], Opcode::IaddIfcout).is_some() { @@ -1784,11 +1752,7 @@ fn lower_insn_to_regs>( // simply use the flags here. let cc = CC::from_intcc(cond_code); - ctx.emit_safepoint(Inst::TrapIf { - trap_code, - srcloc, - cc, - }); + ctx.emit_safepoint(Inst::TrapIf { trap_code, cc }); } else if op == Opcode::Trapif { let cond_code = ctx.data(insn).cond_code().unwrap(); let cc = CC::from_intcc(cond_code); @@ -1797,11 +1761,7 @@ fn lower_insn_to_regs>( let ifcmp = matches_input(ctx, inputs[0], Opcode::Ifcmp).unwrap(); emit_cmp(ctx, ifcmp); - ctx.emit_safepoint(Inst::TrapIf { - trap_code, - srcloc, - cc, - }); + ctx.emit_safepoint(Inst::TrapIf { trap_code, cc }); } else { let cond_code = ctx.data(insn).fp_cond_code().unwrap(); @@ -1809,11 +1769,9 @@ fn lower_insn_to_regs>( let ffcmp = matches_input(ctx, inputs[0], Opcode::Ffcmp).unwrap(); match emit_fcmp(ctx, ffcmp, cond_code, FcmpSpec::Normal) { - FcmpCondResult::Condition(cc) => ctx.emit_safepoint(Inst::TrapIf { - trap_code, - srcloc, - cc, - }), + FcmpCondResult::Condition(cc) => { + ctx.emit_safepoint(Inst::TrapIf { trap_code, cc }) + } FcmpCondResult::AndConditions(cc1, cc2) => { // A bit unfortunate, but materialize the flags in their own register, and // check against this. @@ -1829,21 +1787,12 @@ fn lower_insn_to_regs>( )); ctx.emit_safepoint(Inst::TrapIf { trap_code, - srcloc, cc: CC::NZ, }); } FcmpCondResult::OrConditions(cc1, cc2) => { - ctx.emit_safepoint(Inst::TrapIf { - trap_code, - srcloc, - cc: cc1, - }); - ctx.emit_safepoint(Inst::TrapIf { - trap_code, - srcloc, - cc: cc2, - }); + ctx.emit_safepoint(Inst::TrapIf { trap_code, cc: cc1 }); + ctx.emit_safepoint(Inst::TrapIf { trap_code, cc: cc2 }); } FcmpCondResult::InvertedEqualOrConditions(_, _) => unreachable!(), }; @@ -1920,7 +1869,7 @@ fn lower_insn_to_regs>( ty ), }; - ctx.emit(Inst::xmm_rm_r(sse_op, rhs, dst, None)); + ctx.emit(Inst::xmm_rm_r(sse_op, rhs, dst)); } Opcode::Fmin | Opcode::Fmax => { @@ -2006,18 +1955,18 @@ fn lower_insn_to_regs>( // Copy lhs into tmp let tmp_xmm1 = ctx.alloc_tmp(RegClass::V128, output_ty); - ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(lhs), tmp_xmm1, None)); + ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(lhs), tmp_xmm1)); // Perform min in reverse direction - ctx.emit(Inst::xmm_rm_r(min_op, RegMem::from(dst), tmp_xmm1, None)); + ctx.emit(Inst::xmm_rm_r(min_op, RegMem::from(dst), tmp_xmm1)); // Perform min in original direction - ctx.emit(Inst::xmm_rm_r(min_op, RegMem::reg(lhs), dst, None)); + ctx.emit(Inst::xmm_rm_r(min_op, RegMem::reg(lhs), dst)); // X64 handles propagation of -0's and Nans differently between left and right // operands. After doing the min in both directions, this OR will // guarrentee capture of -0's and Nan in our tmp register - ctx.emit(Inst::xmm_rm_r(or_op, RegMem::from(dst), tmp_xmm1, None)); + ctx.emit(Inst::xmm_rm_r(or_op, RegMem::from(dst), tmp_xmm1)); // Compare unordered to create mask for lanes containing NaNs and then use // that mask to saturate the NaN containing lanes in the tmp register with 1s. @@ -2030,14 +1979,8 @@ fn lower_insn_to_regs>( dst, cond.encode(), false, - None, - )); - ctx.emit(Inst::xmm_rm_r( - or_op, - RegMem::reg(dst.to_reg()), - tmp_xmm1, - None, )); + ctx.emit(Inst::xmm_rm_r(or_op, RegMem::reg(dst.to_reg()), tmp_xmm1)); // The dst register holds a mask for lanes containing NaNs. // We take that mask and shift in preparation for creating a different mask @@ -2049,12 +1992,7 @@ fn lower_insn_to_regs>( // Finally we do a nand with the tmp register to produce the final results // in the dst. - ctx.emit(Inst::xmm_rm_r( - andn_op, - RegMem::reg(tmp_xmm1.to_reg()), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(andn_op, RegMem::reg(tmp_xmm1.to_reg()), dst)); } else { let ( mov_op, @@ -2094,46 +2032,26 @@ fn lower_insn_to_regs>( // Copy lhs into tmp. let tmp_xmm1 = ctx.alloc_tmp(RegClass::V128, types::F32); - ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(lhs), tmp_xmm1, None)); + ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(lhs), tmp_xmm1)); // Perform max in reverse direction. - ctx.emit(Inst::xmm_rm_r( - max_op, - RegMem::reg(dst.to_reg()), - tmp_xmm1, - None, - )); + ctx.emit(Inst::xmm_rm_r(max_op, RegMem::reg(dst.to_reg()), tmp_xmm1)); // Perform max in original direction. - ctx.emit(Inst::xmm_rm_r(max_op, RegMem::reg(lhs), dst, None)); + ctx.emit(Inst::xmm_rm_r(max_op, RegMem::reg(lhs), dst)); // Get the difference between the two results and store in tmp. // Max uses a different approach than min to account for potential // discrepancies with plus/minus 0. - ctx.emit(Inst::xmm_rm_r( - xor_op, - RegMem::reg(tmp_xmm1.to_reg()), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(xor_op, RegMem::reg(tmp_xmm1.to_reg()), dst)); // X64 handles propagation of -0's and Nans differently between left and right // operands. After doing the max in both directions, this OR will // guarentee capture of 0's and Nan in our tmp register. - ctx.emit(Inst::xmm_rm_r( - or_op, - RegMem::reg(dst.to_reg()), - tmp_xmm1, - None, - )); + ctx.emit(Inst::xmm_rm_r(or_op, RegMem::reg(dst.to_reg()), tmp_xmm1)); // Capture NaNs and sign discrepancies. - ctx.emit(Inst::xmm_rm_r( - sub_op, - RegMem::reg(dst.to_reg()), - tmp_xmm1, - None, - )); + ctx.emit(Inst::xmm_rm_r(sub_op, RegMem::reg(dst.to_reg()), tmp_xmm1)); // Compare unordered to create mask for lanes containing NaNs and then use // that mask to saturate the NaN containing lanes in the tmp register with 1s. @@ -2144,7 +2062,6 @@ fn lower_insn_to_regs>( dst, cond.encode(), false, - None, )); // The dst register holds a mask for lanes containing NaNs. @@ -2157,12 +2074,7 @@ fn lower_insn_to_regs>( // Finally we do a nand with the tmp register to produce the final results // in the dst. - ctx.emit(Inst::xmm_rm_r( - andn_op, - RegMem::reg(tmp_xmm1.to_reg()), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(andn_op, RegMem::reg(tmp_xmm1.to_reg()), dst)); } } } @@ -2180,7 +2092,7 @@ fn lower_insn_to_regs>( (types::F64X2, Opcode::FmaxPseudo) => SseOpcode::Maxpd, _ => unimplemented!("unsupported type {} for {}", ty, op), }; - ctx.emit(Inst::xmm_rm_r(sse_opcode, lhs, dst, None)); + ctx.emit(Inst::xmm_rm_r(sse_opcode, lhs, dst)); } Opcode::Sqrt => { @@ -2248,7 +2160,7 @@ fn lower_insn_to_regs>( } }; ctx.emit(Inst::gen_move(dst, src, ty)); - ctx.emit(Inst::xmm_rm_r(opcode, RegMem::from(dst), dst, None)); + ctx.emit(Inst::xmm_rm_r(opcode, RegMem::from(dst), dst)); } } @@ -2334,34 +2246,18 @@ fn lower_insn_to_regs>( ctx.emit(Inst::xmm_rmi_reg(SseOpcode::Psrld, RegMemImm::imm(16), tmp)); // Get the high 16 bits - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Psubd, - RegMem::from(tmp), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Psubd, RegMem::from(tmp), dst)); // Convert the low 16 bits - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Cvtdq2ps, - RegMem::from(tmp), - tmp, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Cvtdq2ps, RegMem::from(tmp), tmp)); // Shift the high bits by 1, convert, and double to get the correct value. ctx.emit(Inst::xmm_rmi_reg(SseOpcode::Psrld, RegMemImm::imm(1), dst)); - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Cvtdq2ps, - RegMem::from(dst), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Cvtdq2ps, RegMem::from(dst), dst)); ctx.emit(Inst::xmm_rm_r( SseOpcode::Addps, RegMem::reg(dst.to_reg()), dst, - None, )); // Add together the two converted values. @@ -2369,7 +2265,6 @@ fn lower_insn_to_regs>( SseOpcode::Addps, RegMem::reg(tmp.to_reg()), dst, - None, )); } } @@ -2404,14 +2299,13 @@ fn lower_insn_to_regs>( let tmp_xmm = ctx.alloc_tmp(RegClass::V128, input_ty); let tmp_gpr = ctx.alloc_tmp(RegClass::I64, output_ty); - let srcloc = ctx.srcloc(insn); if to_signed { ctx.emit(Inst::cvt_float_to_sint_seq( - src_size, dst_size, is_sat, src_copy, dst, tmp_gpr, tmp_xmm, srcloc, + src_size, dst_size, is_sat, src_copy, dst, tmp_gpr, tmp_xmm, )); } else { ctx.emit(Inst::cvt_float_to_uint_seq( - src_size, dst_size, is_sat, src_copy, dst, tmp_gpr, tmp_xmm, srcloc, + src_size, dst_size, is_sat, src_copy, dst, tmp_gpr, tmp_xmm, )); } } else { @@ -2431,13 +2325,11 @@ fn lower_insn_to_regs>( tmp, cond.encode(), false, - None, )); ctx.emit(Inst::xmm_rm_r( SseOpcode::Andps, RegMem::reg(tmp.to_reg()), dst, - None, )); // Sets top bit of tmp if float is positive @@ -2446,7 +2338,6 @@ fn lower_insn_to_regs>( SseOpcode::Pxor, RegMem::reg(dst.to_reg()), tmp, - None, )); // Convert the packed float to packed doubleword. @@ -2454,7 +2345,6 @@ fn lower_insn_to_regs>( SseOpcode::Cvttps2dq, RegMem::reg(dst.to_reg()), dst, - None, )); // Set top bit only if < 0 @@ -2463,7 +2353,6 @@ fn lower_insn_to_regs>( SseOpcode::Pand, RegMem::reg(dst.to_reg()), tmp, - None, )); ctx.emit(Inst::xmm_rmi_reg(SseOpcode::Psrad, RegMemImm::imm(31), tmp)); @@ -2474,7 +2363,6 @@ fn lower_insn_to_regs>( SseOpcode::Pxor, RegMem::reg(tmp.to_reg()), dst, - None, )); } else if op == Opcode::FcvtToUintSat { unimplemented!("f32x4.convert_i32x4_u"); @@ -2567,7 +2455,7 @@ fn lower_insn_to_regs>( ctx.emit(inst); } - ctx.emit(Inst::xmm_rm_r(opcode, src, dst, None)); + ctx.emit(Inst::xmm_rm_r(opcode, src, dst)); } else { // Eventually vector constants should be available in `gen_constant` and this block // can be merged with the one above (TODO). @@ -2588,7 +2476,6 @@ fn lower_insn_to_regs>( tmp, cond.encode(), false, - None, ); ctx.emit(cmpps); @@ -2608,7 +2495,7 @@ fn lower_insn_to_regs>( ctx.emit(shift); // Apply shifted mask (XOR or AND). - let mask = Inst::xmm_rm_r(opcode, RegMem::reg(tmp.to_reg()), dst, None); + let mask = Inst::xmm_rm_r(opcode, RegMem::reg(tmp.to_reg()), dst); ctx.emit(mask); } else { panic!("unexpected type {:?} for Fabs", output_ty); @@ -2661,26 +2548,15 @@ fn lower_insn_to_regs>( }) { ctx.emit(inst); } - ctx.emit(Inst::xmm_mov( - mov_op, - RegMem::reg(tmp_xmm1.to_reg()), - dst, - None, - )); - ctx.emit(Inst::xmm_rm_r(and_not_op, RegMem::reg(lhs), dst, None)); - ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(rhs), tmp_xmm2, None)); + ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(tmp_xmm1.to_reg()), dst)); + ctx.emit(Inst::xmm_rm_r(and_not_op, RegMem::reg(lhs), dst)); + ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(rhs), tmp_xmm2)); ctx.emit(Inst::xmm_rm_r( and_op, RegMem::reg(tmp_xmm1.to_reg()), tmp_xmm2, - None, - )); - ctx.emit(Inst::xmm_rm_r( - or_op, - RegMem::reg(tmp_xmm2.to_reg()), - dst, - None, )); + ctx.emit(Inst::xmm_rm_r(or_op, RegMem::reg(tmp_xmm2.to_reg()), dst)); } Opcode::Ceil | Opcode::Floor | Opcode::Nearest | Opcode::Trunc => { @@ -2783,45 +2659,29 @@ fn lower_insn_to_regs>( _ => unreachable!(), }; - let srcloc = Some(ctx.srcloc(insn)); - let dst = get_output_reg(ctx, outputs[0]); let is_xmm = elem_ty.is_float() || elem_ty.is_vector(); match (sign_extend, is_xmm) { (true, false) => { // The load is sign-extended only when the output size is lower than 64 bits, // so ext-mode is defined in this case. - ctx.emit(Inst::movsx_rm_r( - ext_mode.unwrap(), - RegMem::mem(amode), - dst, - srcloc, - )); + ctx.emit(Inst::movsx_rm_r(ext_mode.unwrap(), RegMem::mem(amode), dst)); } (false, false) => { if elem_ty.bytes() == 8 { // Use a plain load. - ctx.emit(Inst::mov64_m_r(amode, dst, srcloc)) + ctx.emit(Inst::mov64_m_r(amode, dst)) } else { // Use a zero-extended load. - ctx.emit(Inst::movzx_rm_r( - ext_mode.unwrap(), - RegMem::mem(amode), - dst, - srcloc, - )) + ctx.emit(Inst::movzx_rm_r(ext_mode.unwrap(), RegMem::mem(amode), dst)) } } (_, true) => { ctx.emit(match elem_ty { - types::F32 => { - Inst::xmm_mov(SseOpcode::Movss, RegMem::mem(amode), dst, srcloc) - } - types::F64 => { - Inst::xmm_mov(SseOpcode::Movsd, RegMem::mem(amode), dst, srcloc) - } + types::F32 => Inst::xmm_mov(SseOpcode::Movss, RegMem::mem(amode), dst), + types::F64 => Inst::xmm_mov(SseOpcode::Movsd, RegMem::mem(amode), dst), _ if elem_ty.is_vector() && elem_ty.bits() == 128 => { - Inst::xmm_mov(SseOpcode::Movups, RegMem::mem(amode), dst, srcloc) + Inst::xmm_mov(SseOpcode::Movups, RegMem::mem(amode), dst) } // TODO Specialize for different types: MOVUPD, MOVDQU _ => unreachable!("unexpected type for load: {:?}", elem_ty), }); @@ -2873,16 +2733,14 @@ fn lower_insn_to_regs>( let src = put_input_in_reg(ctx, inputs[0]); - let srcloc = Some(ctx.srcloc(insn)); - ctx.emit(match elem_ty { - types::F32 => Inst::xmm_mov_r_m(SseOpcode::Movss, src, addr, srcloc), - types::F64 => Inst::xmm_mov_r_m(SseOpcode::Movsd, src, addr, srcloc), + types::F32 => Inst::xmm_mov_r_m(SseOpcode::Movss, src, addr), + types::F64 => Inst::xmm_mov_r_m(SseOpcode::Movsd, src, addr), _ if elem_ty.is_vector() && elem_ty.bits() == 128 => { // TODO Specialize for different types: MOVUPD, MOVDQU, etc. - Inst::xmm_mov_r_m(SseOpcode::Movups, src, addr, srcloc) + Inst::xmm_mov_r_m(SseOpcode::Movups, src, addr) } - _ => Inst::mov_r_m(elem_ty.bytes() as u8, src, addr, srcloc), + _ => Inst::mov_r_m(elem_ty.bytes() as u8, src, addr), }); } @@ -2901,12 +2759,6 @@ fn lower_insn_to_regs>( let mut arg2 = put_input_in_reg(ctx, inputs[1]); let ty_access = ty.unwrap(); assert!(is_valid_atomic_transaction_ty(ty_access)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; // Make sure that both args are in virtual regs, since in effect we have to do a // parallel copy to get them safely to the AtomicRmwSeq input regs, and that's not @@ -2930,11 +2782,7 @@ fn lower_insn_to_regs>( // Now the AtomicRmwSeq (pseudo-) instruction itself let op = inst_common::AtomicRmwOp::from(ctx.data(insn).atomic_rmw_op().unwrap()); - ctx.emit(Inst::AtomicRmwSeq { - ty: ty_access, - op, - srcloc, - }); + ctx.emit(Inst::AtomicRmwSeq { ty: ty_access, op }); // And finally, copy the preordained AtomicRmwSeq output reg to its destination. ctx.emit(Inst::gen_move(dst, regs::rax(), types::I64)); @@ -2949,12 +2797,6 @@ fn lower_insn_to_regs>( let replacement = put_input_in_reg(ctx, inputs[2]); let ty_access = ty.unwrap(); assert!(is_valid_atomic_transaction_ty(ty_access)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; // Move the expected value into %rax. Because there's only one fixed register on // the input side, we don't have to use `ensure_in_vreg`, as is necessary in the @@ -2968,7 +2810,6 @@ fn lower_insn_to_regs>( ty: ty_access, src: replacement, dst: addr.into(), - srcloc, }); // And finally, copy the old value at the location to its destination reg. ctx.emit(Inst::gen_move(dst, regs::rax(), types::I64)); @@ -2982,23 +2823,17 @@ fn lower_insn_to_regs>( let addr = lower_to_amode(ctx, inputs[0], 0); let ty_access = ty.unwrap(); assert!(is_valid_atomic_transaction_ty(ty_access)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; let rm = RegMem::mem(addr); if ty_access == types::I64 { - ctx.emit(Inst::mov64_rm_r(rm, data, srcloc)); + ctx.emit(Inst::mov64_rm_r(rm, data)); } else { let ext_mode = ExtMode::new(ty_access.bits(), 64).expect(&format!( "invalid extension during AtomicLoad: {} -> {}", ty_access.bits(), 64 )); - ctx.emit(Inst::movzx_rm_r(ext_mode, rm, data, srcloc)); + ctx.emit(Inst::movzx_rm_r(ext_mode, rm, data)); } } @@ -3008,14 +2843,8 @@ fn lower_insn_to_regs>( let addr = lower_to_amode(ctx, inputs[1], 0); let ty_access = ctx.input_ty(insn, 0); assert!(is_valid_atomic_transaction_ty(ty_access)); - let memflags = ctx.memflags(insn).expect("memory flags"); - let srcloc = if !memflags.notrap() { - Some(ctx.srcloc(insn)) - } else { - None - }; - ctx.emit(Inst::mov_r_m(ty_access.bytes() as u8, data, addr, srcloc)); + ctx.emit(Inst::mov_r_m(ty_access.bytes() as u8, data, addr)); ctx.emit(Inst::Fence { kind: FenceKind::MFence, }); @@ -3031,11 +2860,9 @@ fn lower_insn_to_regs>( let dst = get_output_reg(ctx, outputs[0]); let (extname, _) = ctx.call_target(insn).unwrap(); let extname = extname.clone(); - let loc = ctx.srcloc(insn); ctx.emit(Inst::LoadExtName { dst, name: Box::new(extname), - srcloc: loc, offset: 0, }); } @@ -3044,11 +2871,9 @@ fn lower_insn_to_regs>( let dst = get_output_reg(ctx, outputs[0]); let (extname, _, offset) = ctx.symbol_value(insn).unwrap(); let extname = extname.clone(); - let loc = ctx.srcloc(insn); ctx.emit(Inst::LoadExtName { dst, name: Box::new(extname), - srcloc: loc, offset, }); } @@ -3201,8 +3026,8 @@ fn lower_insn_to_regs>( if size == 1 { // Sign-extend operands to 32, then do a cmove of size 4. let lhs_se = ctx.alloc_tmp(RegClass::I64, types::I32); - ctx.emit(Inst::movsx_rm_r(ExtMode::BL, lhs, lhs_se, None)); - ctx.emit(Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rhs), dst, None)); + ctx.emit(Inst::movsx_rm_r(ExtMode::BL, lhs, lhs_se)); + ctx.emit(Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rhs), dst)); ctx.emit(Inst::cmove(4, cc, RegMem::reg(lhs_se.to_reg()), dst)); } else { ctx.emit(Inst::gen_move(dst, rhs, ty)); @@ -3231,7 +3056,6 @@ fn lower_insn_to_regs>( let dividend = put_input_in_reg(ctx, inputs[0]); let dst = get_output_reg(ctx, outputs[0]); - let srcloc = ctx.srcloc(insn); ctx.emit(Inst::gen_move( Writable::from_reg(regs::rax()), dividend, @@ -3262,13 +3086,7 @@ fn lower_insn_to_regs>( 0, Writable::from_reg(regs::rdx()), )); - ctx.emit(Inst::checked_div_or_rem_seq( - kind, - size, - divisor_copy, - tmp, - srcloc, - )); + ctx.emit(Inst::checked_div_or_rem_seq(kind, size, divisor_copy, tmp)); } else { let divisor = input_to_reg_mem(ctx, inputs[1]); @@ -3282,7 +3100,6 @@ fn lower_insn_to_regs>( ExtMode::BL, RegMem::reg(regs::rax()), Writable::from_reg(regs::rax()), - /* infallible */ None, )); } else { // zero for unsigned opcodes. @@ -3294,7 +3111,7 @@ fn lower_insn_to_regs>( } // Emit the actual idiv. - ctx.emit(Inst::div(size, kind.is_signed(), divisor, ctx.srcloc(insn))); + ctx.emit(Inst::div(size, kind.is_signed(), divisor)); } // Move the result back into the destination reg. @@ -3406,12 +3223,7 @@ fn lower_insn_to_regs>( // After loading the constructed mask in a temporary register, we use this to // shuffle the `dst` register (remember that, in this case, it is the same as // `src` so we disregard this register). - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pshufb, - RegMem::from(tmp), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::from(tmp), dst)); } else { // If `lhs` and `rhs` are different, we must shuffle each separately and then OR // them together. This is necessary due to PSHUFB semantics. As in the case above, @@ -3424,12 +3236,7 @@ fn lower_insn_to_regs>( let constant = ctx.use_constant(VCodeConstantData::Generated(constructed_mask)); let tmp1 = ctx.alloc_tmp(RegClass::V128, types::I8X16); ctx.emit(Inst::xmm_load_const(constant, tmp1, ty)); - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pshufb, - RegMem::from(tmp1), - tmp0, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::from(tmp1), tmp0)); // PSHUFB the second argument, placing zeroes for unused lanes. let constructed_mask = mask @@ -3440,21 +3247,11 @@ fn lower_insn_to_regs>( let constant = ctx.use_constant(VCodeConstantData::Generated(constructed_mask)); let tmp2 = ctx.alloc_tmp(RegClass::V128, types::I8X16); ctx.emit(Inst::xmm_load_const(constant, tmp2, ty)); - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pshufb, - RegMem::from(tmp2), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::from(tmp2), dst)); // OR the shuffled registers (the mechanism and lane-size for OR-ing the registers // is not important). - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Orps, - RegMem::from(tmp0), - dst, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Orps, RegMem::from(tmp0), dst)); // TODO when AVX512 is enabled we should replace this sequence with a single VPERMB } @@ -3489,7 +3286,6 @@ fn lower_insn_to_regs>( SseOpcode::Paddusb, RegMem::from(zero_mask), swizzle_mask, - None, )); // Shuffle `dst` using the fixed-up `swizzle_mask`. @@ -3497,7 +3293,6 @@ fn lower_insn_to_regs>( SseOpcode::Pshufb, RegMem::from(swizzle_mask), dst, - None, )); } @@ -3517,7 +3312,7 @@ fn lower_insn_to_regs>( debug_assert!(lane < ty.lane_count() as u8); ctx.emit(Inst::gen_move(dst, in_vec, ty)); - emit_insert_lane(ctx, src, dst, lane, ty.lane_type(), None); + emit_insert_lane(ctx, src, dst, lane, ty.lane_type()); } Opcode::Extractlane => { @@ -3543,7 +3338,7 @@ fn lower_insn_to_regs>( _ => panic!("Unable to extractlane for lane size: {}", ty.lane_bits()), }; let src = RegMem::reg(src); - ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, lane, w_bit, None)); + ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, lane, w_bit)); } else { if lane == 0 { // Remove the extractlane instruction, leaving the float where it is. The upper @@ -3565,7 +3360,7 @@ fn lower_insn_to_regs>( _ => unreachable!(), }; let src = RegMem::reg(src); - ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, mask, false, None)); + ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, mask, false)); } } } @@ -3576,12 +3371,12 @@ fn lower_insn_to_regs>( let src_ty = ctx.input_ty(insn, 0); assert!(src_ty.bits() < 128); - let (src, srcloc) = match op { - Opcode::Splat => (input_to_reg_mem(ctx, inputs[0]), None), + let src = match op { + Opcode::Splat => input_to_reg_mem(ctx, inputs[0]), Opcode::LoadSplat => { let offset = ctx.data(insn).load_store_offset().unwrap(); let amode = lower_to_amode(ctx, inputs[0], offset); - (RegMem::mem(amode), Some(ctx.srcloc(insn))) + RegMem::mem(amode) } _ => unreachable!(), }; @@ -3596,26 +3391,16 @@ fn lower_insn_to_regs>( // and VPBROADCAST*. match ty.lane_bits() { 8 => { - emit_insert_lane(ctx, src, dst, 0, ty.lane_type(), srcloc); + emit_insert_lane(ctx, src, dst, 0, ty.lane_type()); // Initialize a register with all 0s. let tmp = ctx.alloc_tmp(RegClass::V128, ty); - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pxor, - RegMem::from(tmp), - tmp, - srcloc, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), tmp)); // Shuffle the lowest byte lane to all other lanes. - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pshufb, - RegMem::from(tmp), - dst, - srcloc, - )) + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::from(tmp), dst)) } 16 => { - emit_insert_lane(ctx, src.clone(), dst, 0, ty.lane_type(), srcloc); - emit_insert_lane(ctx, src, dst, 1, ty.lane_type(), srcloc); + emit_insert_lane(ctx, src.clone(), dst, 0, ty.lane_type()); + emit_insert_lane(ctx, src, dst, 1, ty.lane_type()); // Shuffle the lowest two lanes to all other lanes. ctx.emit(Inst::xmm_rm_r_imm( SseOpcode::Pshufd, @@ -3623,11 +3408,10 @@ fn lower_insn_to_regs>( dst, 0, false, - srcloc, )) } 32 => { - emit_insert_lane(ctx, src, dst, 0, ty.lane_type(), srcloc); + emit_insert_lane(ctx, src, dst, 0, ty.lane_type()); // Shuffle the lowest lane to all other lanes. ctx.emit(Inst::xmm_rm_r_imm( SseOpcode::Pshufd, @@ -3635,12 +3419,11 @@ fn lower_insn_to_regs>( dst, 0, false, - srcloc, )) } 64 => { - emit_insert_lane(ctx, src.clone(), dst, 0, ty.lane_type(), srcloc); - emit_insert_lane(ctx, src, dst, 1, ty.lane_type(), srcloc); + emit_insert_lane(ctx, src.clone(), dst, 0, ty.lane_type()); + emit_insert_lane(ctx, src, dst, 1, ty.lane_type()); } _ => panic!("Invalid type to splat: {}", ty), } @@ -3674,14 +3457,9 @@ fn lower_insn_to_regs>( // Initialize a register with all 0s. let tmp = ctx.alloc_tmp(RegClass::V128, ty); - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Pxor, - RegMem::from(tmp), - tmp, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), tmp)); // Compare to see what lanes are filled with all 1s. - ctx.emit(Inst::xmm_rm_r(eq(src_ty), src, tmp, None)); + ctx.emit(Inst::xmm_rm_r(eq(src_ty), src, tmp)); // Set the ZF if the result is all zeroes. ctx.emit(Inst::xmm_cmp_rm_r( SseOpcode::Ptest, @@ -3726,12 +3504,7 @@ fn lower_insn_to_regs>( // - shift away the bottom 8 high bits to remove the duplicates. let tmp = ctx.alloc_tmp(RegClass::V128, src_ty); ctx.emit(Inst::gen_move(tmp, src, src_ty)); - ctx.emit(Inst::xmm_rm_r( - SseOpcode::Packsswb, - RegMem::reg(src), - tmp, - None, - )); + ctx.emit(Inst::xmm_rm_r(SseOpcode::Packsswb, RegMem::reg(src), tmp)); ctx.emit(Inst::xmm_to_gpr( SseOpcode::Pmovmskb, tmp.to_reg(), diff --git a/cranelift/codegen/src/machinst/abi_impl.rs b/cranelift/codegen/src/machinst/abi_impl.rs index e967e939d1..e47379da37 100644 --- a/cranelift/codegen/src/machinst/abi_impl.rs +++ b/cranelift/codegen/src/machinst/abi_impl.rs @@ -111,7 +111,7 @@ use super::abi::*; use crate::binemit::StackMap; use crate::ir::types::*; -use crate::ir::{ArgumentExtension, SourceLoc, StackSlot}; +use crate::ir::{ArgumentExtension, StackSlot}; use crate::machinst::*; use crate::settings; use crate::CodegenResult; @@ -350,7 +350,6 @@ pub trait ABIMachineSpec { dest: &CallDest, uses: Vec, defs: Vec>, - loc: SourceLoc, opcode: ir::Opcode, tmp: Writable, callee_conv: isa::CallConv, @@ -1102,8 +1101,6 @@ pub struct ABICallerImpl { defs: Vec>, /// Call destination. dest: CallDest, - /// Location of callsite. - loc: ir::SourceLoc, /// Actual call opcode; used to distinguish various types of calls. opcode: ir::Opcode, /// Caller's calling convention. @@ -1127,7 +1124,6 @@ impl ABICallerImpl { sig: &ir::Signature, extname: &ir::ExternalName, dist: RelocDistance, - loc: ir::SourceLoc, caller_conv: isa::CallConv, ) -> CodegenResult> { let sig = ABISig::from_func_sig::(sig)?; @@ -1137,7 +1133,6 @@ impl ABICallerImpl { uses, defs, dest: CallDest::ExtName(extname.clone(), dist), - loc, opcode: ir::Opcode::Call, caller_conv, _mach: PhantomData, @@ -1149,7 +1144,6 @@ impl ABICallerImpl { pub fn from_ptr( sig: &ir::Signature, ptr: Reg, - loc: ir::SourceLoc, opcode: ir::Opcode, caller_conv: isa::CallConv, ) -> CodegenResult> { @@ -1160,7 +1154,6 @@ impl ABICallerImpl { uses, defs, dest: CallDest::Reg(ptr), - loc, opcode, caller_conv, _mach: PhantomData, @@ -1311,7 +1304,6 @@ impl ABICaller for ABICallerImpl { &self.dest, uses, defs, - self.loc, self.opcode, tmp, self.sig.call_conv, diff --git a/cranelift/codegen/src/machinst/buffer.rs b/cranelift/codegen/src/machinst/buffer.rs index 0cc9d240b7..b2187a9b68 100644 --- a/cranelift/codegen/src/machinst/buffer.rs +++ b/cranelift/codegen/src/machinst/buffer.rs @@ -1535,7 +1535,7 @@ mod test { buf.bind_label(label(1)); let inst = Inst::Udf { - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, }; inst.emit(&mut buf, &info, &mut state); @@ -1551,7 +1551,7 @@ mod test { let mut state = Default::default(); let inst = Inst::TrapIf { kind: CondBrKind::NotZero(xreg(0)), - trap_info: (SourceLoc::default(), TrapCode::Interrupt), + trap_code: TrapCode::Interrupt, }; inst.emit(&mut buf2, &info, &mut state); let inst = Inst::Nop4; diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index 83b3c6f83b..4b12f2fd1d 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -98,7 +98,7 @@ use crate::binemit::{CodeInfo, CodeOffset, StackMap}; use crate::ir::condcodes::IntCC; -use crate::ir::{Function, Type}; +use crate::ir::{Function, SourceLoc, Type}; use crate::isa::unwind::input as unwind_input; use crate::result::CodegenResult; use crate::settings::Flags; @@ -302,6 +302,9 @@ pub trait MachInstEmitState: Default + Clone + Debug { /// Update the emission state before emitting an instruction that is a /// safepoint. fn pre_safepoint(&mut self, _stack_map: StackMap) {} + /// Update the emission state to indicate instructions are associated with a + /// particular SourceLoc. + fn pre_sourceloc(&mut self, _srcloc: SourceLoc) {} } /// The result of a `MachBackend::compile_function()` call. Contains machine diff --git a/cranelift/codegen/src/machinst/vcode.rs b/cranelift/codegen/src/machinst/vcode.rs index 1a34ae988a..1ca1b25ce3 100644 --- a/cranelift/codegen/src/machinst/vcode.rs +++ b/cranelift/codegen/src/machinst/vcode.rs @@ -509,6 +509,7 @@ impl VCode { buffer.start_srcloc(srcloc); cur_srcloc = Some(srcloc); } + state.pre_sourceloc(cur_srcloc.unwrap_or(SourceLoc::default())); if safepoint_idx < self.safepoint_insns.len() && self.safepoint_insns[safepoint_idx] == iix