aarch64: Add sbcs instruction encodings

2021-06-09 09:15:15 +01:00
parent 61f07d79a7
commit 4d085d8fbf
3 changed files with 27 additions and 0 deletions
--- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
@@ -130,6 +130,26 @@ fn test_aarch64_binemit() {
        "A40006DA",
        "sbc x4, x5, x6",
    ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::SbcS32,
+            rd: writable_xreg(1),
+            rn: xreg(2),
+            rm: xreg(3),
+        },
+        "4100037A",
+        "sbcs w1, w2, w3",
+    ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::SbcS64,
+            rd: writable_xreg(4),
+            rn: xreg(5),
+            rm: xreg(6),
+        },
+        "A40006FA",
+        "sbcs x4, x5, x6",
+    ));

    insns.push((
        Inst::AluRRR {