diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
index ccde5e0385..157ea6ebee 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -605,6 +605,8 @@ impl MachInstEmit for Inst {
                     ALUOp::Sub64 => 0b11001011_000,
                     ALUOp::Sbc32 => 0b01011010_000,
                     ALUOp::Sbc64 => 0b11011010_000,
+                    ALUOp::SbcS32 => 0b01111010_000,
+                    ALUOp::SbcS64 => 0b11111010_000,
                     ALUOp::Orr32 => 0b00101010_000,
                     ALUOp::Orr64 => 0b10101010_000,
                     ALUOp::And32 => 0b00001010_000,
diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
index f6735397d1..f48a689e13 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
@@ -130,6 +130,26 @@ fn test_aarch64_binemit() {
         "A40006DA",
         "sbc x4, x5, x6",
     ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::SbcS32,
+            rd: writable_xreg(1),
+            rn: xreg(2),
+            rm: xreg(3),
+        },
+        "4100037A",
+        "sbcs w1, w2, w3",
+    ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::SbcS64,
+            rd: writable_xreg(4),
+            rn: xreg(5),
+            rm: xreg(6),
+        },
+        "A40006FA",
+        "sbcs x4, x5, x6",
+    ));
 
     insns.push((
         Inst::AluRRR {
diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
index 1b6534de31..854e0b603c 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -93,6 +93,9 @@ pub enum ALUOp {
     /// Subtract with carry
     Sbc32,
     Sbc64,
+    /// Subtract with carry, settings flags
+    SbcS32,
+    SbcS64,
 }
 
 /// An ALU operation with three arguments.
@@ -3219,6 +3222,8 @@ impl Inst {
                 ALUOp::AdcS64 => ("adcs", OperandSize::Size64),
                 ALUOp::Sbc32 => ("sbc", OperandSize::Size32),
                 ALUOp::Sbc64 => ("sbc", OperandSize::Size64),
+                ALUOp::SbcS32 => ("sbcs", OperandSize::Size32),
+                ALUOp::SbcS64 => ("sbcs", OperandSize::Size64),
             }
         }