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Add Intel regmove encodings for floating point types.

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This commit is contained in:
Jakob Stoklund Olesen
2017-09-27 12:36:27 -07:00
parent 1fe7890700
commit 44eab3e158
3 changed files with 20 additions and 0 deletions
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2
lib/cretonne/meta/isa/intel/encodings.py
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@@ -358,6 +358,8 @@ I64.enc(base.bitcast.i64.f64, *r.rfumr.rex(0x66, 0x0f, 0x7e, w=1))
# movaps
enc_flt(base.copy.f32, r.furm, 0x0f, 0x28)
enc_flt(base.copy.f64, r.furm, 0x0f, 0x28)
enc_flt(base.regmove.f32, r.frmov, 0x0f, 0x28)
enc_flt(base.regmove.f64, r.frmov, 0x0f, 0x28)
# cvtsi2ss
enc_i32_i64(base.fcvt_from_sint.f32, r.frurm, 0xf3, 0x0f, 0x2a)

8
lib/cretonne/meta/isa/intel/recipes.py
View File

@@ -321,6 +321,14 @@ rmov = TailRecipe(
modrm_rr(dst, src, sink);
''')
# XX /r, for regmove instructions (FPR version, RM encoded).
frmov = TailRecipe(
'frmov', RegMove, size=1, ins=FPR, outs=(),
emit='''
PUT_OP(bits, rex2(src, dst), sink);
modrm_rr(src, dst, sink);
''')
# XX /n with one arg in %rcx, for shifts.
rc = TailRecipe(
'rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0,