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winch: Use aarch64 backend for code emission. (#5652)

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This patch introduces basic aarch64 code generation by using
`cranelift-codegen`'s backend.

This commit *does not*:

* Change the semantics of the code generation
* Adds support for other Wasm instructions

The most notable change in this patch is how addressing modes are handled at the
MacroAssembler layer: instead of having a canonical address representation, this
patch introduces the addressing mode as an associated type in the
MacroAssembler trait. This approach has the advantage that gives each ISA enough
flexiblity to describe the addressing modes and their constraints in isolation
without having to worry on how a particular addressing mode is going to affect
other ISAs. In the case of Aarch64 this becomes useful to describe indexed
addressing modes (particularly from the stack pointer).

This patch uses the concept of a shadow stack pointer (x28) as a workaround to
Aarch64's stack pointer 16-byte alignment. This constraint is enforced by:

* Introducing specialized addressing modes when using the real stack pointer; this
enables auditing when the real stack pointer is used. As of this change, the
real stack pointer is only used in the function's prologue and epilogue.

* Asserting that the real stack pointer is not used as a base for addressing
modes.

* Ensuring that at any point during the code generation process where the stack
pointer changes (e.g. when stack space is allocated / deallocated) the value of
the real stack pointer is copied into the shadow stack pointer.
This commit is contained in:
Saúl Cabrera
2023-02-02 17:24:11 -05:00
committed by GitHub
parent a2a0a9ef5b
commit 426c49b8e3
18 changed files with 840 additions and 65 deletions
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12
winch/codegen/src/isa/x64/asm.rs
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@@ -1,6 +1,6 @@
//! Assembler library implementation for x64.
use crate::{abi::Address, isa::reg::Reg, masm::OperandSize};
use crate::{isa::reg::Reg, masm::OperandSize};
use cranelift_codegen::{
isa::x64::{
args::{
@@ -12,6 +12,8 @@ use cranelift_codegen::{
settings, Final, MachBuffer, MachBufferFinalized, MachInstEmit, Writable,
};
use super::address::Address;
/// A x64 instruction operand.
#[derive(Debug, Copy, Clone)]
pub(crate) enum Operand {
@@ -95,14 +97,16 @@ impl Assembler {
match &(src, dst) {
(Reg(lhs), Reg(rhs)) => self.mov_rr(*lhs, *rhs, size),
(Reg(lhs), Mem(addr)) => match addr {
Address::Base { base, imm } => self.mov_rm(*lhs, *base, *imm, size),
Address::Offset { base, offset: imm } => self.mov_rm(*lhs, *base, *imm, size),
},
(Imm(imm), Mem(addr)) => match addr {
Address::Base { base, imm: disp } => self.mov_im(*imm as u64, *base, *disp, size),
Address::Offset { base, offset: disp } => {
self.mov_im(*imm as u64, *base, *disp, size)
}
},
(Imm(imm), Reg(reg)) => self.mov_ir(*imm as u64, *reg, size),
(Mem(addr), Reg(reg)) => match addr {
Address::Base { base, imm } => self.mov_mr(*base, *imm, *reg, size),
Address::Offset { base, offset: imm } => self.mov_mr(*base, *imm, *reg, size),
},
_ => panic!(