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cranelift: Update assertions to indicate that rotl is fully ported to ISLE on x64

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This commit is contained in:
Nick Fitzgerald
2022-01-13 13:19:51 -08:00
parent 4e34dd8239
commit 4120e40318
1 changed files with 3 additions and 6 deletions
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9
cranelift/codegen/src/isa/x64/lower.rs
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@@ -1541,17 +1541,14 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
| Opcode::Vselect | Opcode::Vselect
| Opcode::Ushr | Opcode::Ushr
| Opcode::Sshr | Opcode::Sshr
| Opcode::Ishl => implemented_in_isle(ctx), | Opcode::Ishl
| Opcode::Rotl => implemented_in_isle(ctx),
Opcode::Rotl | Opcode::Rotr => { Opcode::Rotr => {
let dst_ty = ctx.output_ty(insn, 0); let dst_ty = ctx.output_ty(insn, 0);
debug_assert_eq!(ctx.input_ty(insn, 0), dst_ty); debug_assert_eq!(ctx.input_ty(insn, 0), dst_ty);
if !dst_ty.is_vector() && dst_ty.bits() <= 64 { if !dst_ty.is_vector() && dst_ty.bits() <= 64 {
if op != Opcode::Rotr {
implemented_in_isle(ctx);
}
// Scalar shifts on x86 have various encodings: // Scalar shifts on x86 have various encodings:
// - shift by one bit, e.g. `SAL r/m8, 1` (not used here) // - shift by one bit, e.g. `SAL r/m8, 1` (not used here)
// - shift by an immediate amount, e.g. `SAL r/m8, imm8` // - shift by an immediate amount, e.g. `SAL r/m8, imm8`