From 4120e4031820598dcb7163333aeb7b58e69381d3 Mon Sep 17 00:00:00 2001 From: Nick Fitzgerald Date: Thu, 13 Jan 2022 13:19:51 -0800 Subject: [PATCH] cranelift: Update assertions to indicate that `rotl` is fully ported to ISLE on x64 --- cranelift/codegen/src/isa/x64/lower.rs | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index 606b208c17..576a3fdf38 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -1541,17 +1541,14 @@ fn lower_insn_to_regs>( | Opcode::Vselect | Opcode::Ushr | Opcode::Sshr - | Opcode::Ishl => implemented_in_isle(ctx), + | Opcode::Ishl + | Opcode::Rotl => implemented_in_isle(ctx), - Opcode::Rotl | Opcode::Rotr => { + Opcode::Rotr => { let dst_ty = ctx.output_ty(insn, 0); debug_assert_eq!(ctx.input_ty(insn, 0), dst_ty); if !dst_ty.is_vector() && dst_ty.bits() <= 64 { - if op != Opcode::Rotr { - implemented_in_isle(ctx); - } - // Scalar shifts on x86 have various encodings: // - shift by one bit, e.g. `SAL r/m8, 1` (not used here) // - shift by an immediate amount, e.g. `SAL r/m8, imm8`