remove unsigned_add_overflow_condition (#6199)

cranelift/codegen/src/isa/aarch64/mod.rs

@@ -1,7 +1,6 @@
 //! ARM 64-bit Instruction Set Architecture.
 
 use crate::dominator_tree::DominatorTree;
-use crate::ir::condcodes::IntCC;
 use crate::ir::{Function, Type};
 use crate::isa::aarch64::settings as aarch64_settings;
 #[cfg(feature = "unwind")]
@@ -134,12 +133,6 @@ impl TargetIsa for AArch64Backend {
         16
     }
 
-    fn unsigned_add_overflow_condition(&self) -> IntCC {
-        // Unsigned `>=`; this corresponds to the carry flag set on aarch64, which happens on
-        // overflow of an add.
-        IntCC::UnsignedGreaterThanOrEqual
-    }
-
     #[cfg(feature = "unwind")]
     fn emit_unwind_info(
         &self,

cranelift/codegen/src/isa/mod.rs

@@ -286,9 +286,6 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
         Err(RegisterMappingError::UnsupportedArchitecture)
     }
 
-    /// IntCC condition for Unsigned Addition Overflow (Carry).
-    fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC;
-
     /// Creates unwind information for the function.
     ///
     /// Returns `None` if there is no unwind information for the function.

cranelift/codegen/src/isa/riscv64/mod.rs

@@ -2,7 +2,6 @@
 
 use crate::dominator_tree::DominatorTree;
 use crate::ir;
-use crate::ir::condcodes::IntCC;
 use crate::ir::Function;
 
 use crate::isa::riscv64::settings as riscv_settings;
@@ -130,10 +129,6 @@ impl TargetIsa for Riscv64Backend {
         self.isa_flags.iter().collect()
     }
 
-    fn unsigned_add_overflow_condition(&self) -> IntCC {
-        IntCC::UnsignedGreaterThanOrEqual
-    }
-
     #[cfg(feature = "unwind")]
     fn emit_unwind_info(
         &self,

cranelift/codegen/src/isa/s390x/mod.rs

@@ -1,7 +1,6 @@
 //! IBM Z 64-bit Instruction Set Architecture.
 
 use crate::dominator_tree::DominatorTree;
-use crate::ir::condcodes::IntCC;
 use crate::ir::{Function, Type};
 use crate::isa::s390x::settings as s390x_settings;
 #[cfg(feature = "unwind")]
@@ -131,15 +130,6 @@ impl TargetIsa for S390xBackend {
         16
     }
 
-    fn unsigned_add_overflow_condition(&self) -> IntCC {
-        // The ADD LOGICAL family of instructions set the condition code
-        // differently from normal comparisons, in a way that cannot be
-        // represented by any of the standard IntCC values.  So we use a
-        // dummy value here, which gets remapped to the correct condition
-        // code mask during lowering.
-        IntCC::UnsignedGreaterThan
-    }
-
     #[cfg(feature = "unwind")]
     fn emit_unwind_info(
         &self,

cranelift/codegen/src/isa/x64/mod.rs

@@ -4,7 +4,7 @@ pub use self::inst::{args, CallInfo, EmitInfo, EmitState, Inst};
 
 use super::{OwnedTargetIsa, TargetIsa};
 use crate::dominator_tree::DominatorTree;
-use crate::ir::{condcodes::IntCC, Function, Type};
+use crate::ir::{Function, Type};
 #[cfg(feature = "unwind")]
 use crate::isa::unwind::systemv;
 use crate::isa::x64::{inst::regs::create_reg_env_systemv, settings as x64_settings};
@@ -124,12 +124,6 @@ impl TargetIsa for X64Backend {
         &self.triple
     }
 
-    fn unsigned_add_overflow_condition(&self) -> IntCC {
-        // Unsigned `<`; this corresponds to the carry flag set on x86, which
-        // indicates an add has overflowed.
-        IntCC::UnsignedLessThan
-    }
-
     #[cfg(feature = "unwind")]
     fn emit_unwind_info(
         &self,