diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index a5403ca5c3..1c3f2809c4 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -1,7 +1,6 @@ //! ARM 64-bit Instruction Set Architecture. use crate::dominator_tree::DominatorTree; -use crate::ir::condcodes::IntCC; use crate::ir::{Function, Type}; use crate::isa::aarch64::settings as aarch64_settings; #[cfg(feature = "unwind")] @@ -134,12 +133,6 @@ impl TargetIsa for AArch64Backend { 16 } - fn unsigned_add_overflow_condition(&self) -> IntCC { - // Unsigned `>=`; this corresponds to the carry flag set on aarch64, which happens on - // overflow of an add. - IntCC::UnsignedGreaterThanOrEqual - } - #[cfg(feature = "unwind")] fn emit_unwind_info( &self, diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index da778c9b61..6ea98af985 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -286,9 +286,6 @@ pub trait TargetIsa: fmt::Display + Send + Sync { Err(RegisterMappingError::UnsupportedArchitecture) } - /// IntCC condition for Unsigned Addition Overflow (Carry). - fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC; - /// Creates unwind information for the function. /// /// Returns `None` if there is no unwind information for the function. diff --git a/cranelift/codegen/src/isa/riscv64/mod.rs b/cranelift/codegen/src/isa/riscv64/mod.rs index f567481e92..8babe53e93 100644 --- a/cranelift/codegen/src/isa/riscv64/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/mod.rs @@ -2,7 +2,6 @@ use crate::dominator_tree::DominatorTree; use crate::ir; -use crate::ir::condcodes::IntCC; use crate::ir::Function; use crate::isa::riscv64::settings as riscv_settings; @@ -130,10 +129,6 @@ impl TargetIsa for Riscv64Backend { self.isa_flags.iter().collect() } - fn unsigned_add_overflow_condition(&self) -> IntCC { - IntCC::UnsignedGreaterThanOrEqual - } - #[cfg(feature = "unwind")] fn emit_unwind_info( &self, diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index d2705e78cc..bcd3c733b0 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -1,7 +1,6 @@ //! IBM Z 64-bit Instruction Set Architecture. use crate::dominator_tree::DominatorTree; -use crate::ir::condcodes::IntCC; use crate::ir::{Function, Type}; use crate::isa::s390x::settings as s390x_settings; #[cfg(feature = "unwind")] @@ -131,15 +130,6 @@ impl TargetIsa for S390xBackend { 16 } - fn unsigned_add_overflow_condition(&self) -> IntCC { - // The ADD LOGICAL family of instructions set the condition code - // differently from normal comparisons, in a way that cannot be - // represented by any of the standard IntCC values. So we use a - // dummy value here, which gets remapped to the correct condition - // code mask during lowering. - IntCC::UnsignedGreaterThan - } - #[cfg(feature = "unwind")] fn emit_unwind_info( &self, diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 029c7f9f57..51556a892f 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -4,7 +4,7 @@ pub use self::inst::{args, CallInfo, EmitInfo, EmitState, Inst}; use super::{OwnedTargetIsa, TargetIsa}; use crate::dominator_tree::DominatorTree; -use crate::ir::{condcodes::IntCC, Function, Type}; +use crate::ir::{Function, Type}; #[cfg(feature = "unwind")] use crate::isa::unwind::systemv; use crate::isa::x64::{inst::regs::create_reg_env_systemv, settings as x64_settings}; @@ -124,12 +124,6 @@ impl TargetIsa for X64Backend { &self.triple } - fn unsigned_add_overflow_condition(&self) -> IntCC { - // Unsigned `<`; this corresponds to the carry flag set on x86, which - // indicates an add has overflowed. - IntCC::UnsignedLessThan - } - #[cfg(feature = "unwind")] fn emit_unwind_info( &self, diff --git a/cranelift/filetests/src/test_wasm/env.rs b/cranelift/filetests/src/test_wasm/env.rs index 8a0ea656b9..23ca9bac81 100644 --- a/cranelift/filetests/src/test_wasm/env.rs +++ b/cranelift/filetests/src/test_wasm/env.rs @@ -604,10 +604,6 @@ impl<'a> FuncEnvironment for FuncEnv<'a> { .translate_atomic_notify(pos, index, heap, addr, count) } - fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC { - self.inner.unsigned_add_overflow_condition() - } - fn heaps( &self, ) -> &cranelift_codegen::entity::PrimaryMap diff --git a/cranelift/wasm/src/environ/dummy.rs b/cranelift/wasm/src/environ/dummy.rs index 030e0c9ed9..d17eda8183 100644 --- a/cranelift/wasm/src/environ/dummy.rs +++ b/cranelift/wasm/src/environ/dummy.rs @@ -655,10 +655,6 @@ impl<'dummy_environment> FuncEnvironment for DummyFuncEnvironment<'dummy_environ ) -> WasmResult { Ok(pos.ins().iconst(I32, 0)) } - - fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC { - unimplemented!() - } } impl TargetEnvironment for DummyEnvironment { diff --git a/cranelift/wasm/src/environ/spec.rs b/cranelift/wasm/src/environ/spec.rs index 03121c8c9c..63712c3b95 100644 --- a/cranelift/wasm/src/environ/spec.rs +++ b/cranelift/wasm/src/environ/spec.rs @@ -522,10 +522,6 @@ pub trait FuncEnvironment: TargetEnvironment { Ok(()) } - /// Returns the target ISA's condition to check for unsigned addition - /// overflowing. - fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC; - /// Whether or not to force relaxed simd instructions to have deterministic /// lowerings meaning they will produce the same results across all hosts, /// regardless of the cost to performance. diff --git a/crates/cranelift/src/func_environ.rs b/crates/cranelift/src/func_environ.rs index 55272b1b98..305d123551 100644 --- a/crates/cranelift/src/func_environ.rs +++ b/crates/cranelift/src/func_environ.rs @@ -2150,10 +2150,6 @@ impl<'module_environment> cranelift_wasm::FuncEnvironment for FuncEnvironment<'m Ok(()) } - fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC { - self.isa.unsigned_add_overflow_condition() - } - fn relaxed_simd_deterministic(&self) -> bool { self.tunables.relaxed_simd_deterministic }