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x64: special case 0 to use xor in Inst::gen_constant for i128s

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This commit is contained in:
Nick Fitzgerald
2021-11-10 15:57:58 -08:00
parent b5105c025c
commit 33fcd6b4a5
2 changed files with 30 additions and 16 deletions
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34
cranelift/codegen/src/isa/x64/inst/mod.rs
View File

@@ -3237,16 +3237,30 @@ impl MachInst for Inst {
) -> SmallVec<[Self; 4]> { ) -> SmallVec<[Self; 4]> {
let mut ret = SmallVec::new(); let mut ret = SmallVec::new();
if ty == types::I128 { if ty == types::I128 {
ret.push(Inst::imm( let lo = value as u64;
OperandSize::Size64, let hi = (value >> 64) as u64;
value as u64, let lo_reg = to_regs.regs()[0];
to_regs.regs()[0], let hi_reg = to_regs.regs()[1];
)); if lo == 0 {
ret.push(Inst::imm( ret.push(Inst::alu_rmi_r(
OperandSize::Size64, OperandSize::Size64,
(value >> 64) as u64, AluRmiROpcode::Xor,
to_regs.regs()[1], RegMemImm::reg(lo_reg.to_reg()),
)); lo_reg,
));
} else {
ret.push(Inst::imm(OperandSize::Size64, lo, lo_reg));
}
if hi == 0 {
ret.push(Inst::alu_rmi_r(
OperandSize::Size64,
AluRmiROpcode::Xor,
RegMemImm::reg(hi_reg.to_reg()),
hi_reg,
));
} else {
ret.push(Inst::imm(OperandSize::Size64, hi, hi_reg));
}
} else { } else {
let to_reg = to_regs let to_reg = to_regs
.only_reg() .only_reg()

12
cranelift/filetests/filetests/isa/x64/i128.clif
View File

@@ -702,10 +702,10 @@ block2(v6: i128):
; nextln: testb $$1, %dl ; nextln: testb $$1, %dl
; nextln: jnz label1; j label2 ; nextln: jnz label1; j label2
; check: Block 1: ; check: Block 1:
; check: movl $$0, %edi ; check: xorq %rdi, %rdi
; nextln: movl $$0, %esi ; nextln: xorq %rsi, %rsi
; nextln: movl $$1, %ecx ; nextln: movl $$1, %ecx
; nextln: movl $$0, %eax ; nextln: xorq %rax, %rax
; nextln: addq %rcx, %rdi ; nextln: addq %rcx, %rdi
; nextln: adcq %rax, %rsi ; nextln: adcq %rax, %rsi
; nextln: movq %rdi, %rax ; nextln: movq %rdi, %rax
@@ -714,10 +714,10 @@ block2(v6: i128):
; nextln: popq %rbp ; nextln: popq %rbp
; nextln: ret ; nextln: ret
; check: Block 2: ; check: Block 2:
; check: movl $$0, %edi ; check: xorq %rdi, %rdi
; nextln: movl $$0, %esi ; nextln: xorq %rsi, %rsi
; nextln: movl $$2, %ecx ; nextln: movl $$2, %ecx
; nextln: movl $$0, %eax ; nextln: xorq %rax, %rax
; nextln: addq %rcx, %rdi ; nextln: addq %rcx, %rdi
; nextln: adcq %rax, %rsi ; nextln: adcq %rax, %rsi
; nextln: movq %rdi, %rax ; nextln: movq %rdi, %rax