From 33fcd6b4a50f2a63a05fd5e707914d904ce41587 Mon Sep 17 00:00:00 2001
From: Nick Fitzgerald <fitzgen@gmail.com>
Date: Wed, 10 Nov 2021 15:57:58 -0800
Subject: [PATCH] x64: special case `0` to use `xor` in `Inst::gen_constant`
 for `i128`s

---
 cranelift/codegen/src/isa/x64/inst/mod.rs     | 34 +++++++++++++------
 .../filetests/filetests/isa/x64/i128.clif     | 12 +++----
 2 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs
index 5d67835941..d011cd2b97 100644
--- a/cranelift/codegen/src/isa/x64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/x64/inst/mod.rs
@@ -3237,16 +3237,30 @@ impl MachInst for Inst {
     ) -> SmallVec<[Self; 4]> {
         let mut ret = SmallVec::new();
         if ty == types::I128 {
-            ret.push(Inst::imm(
-                OperandSize::Size64,
-                value as u64,
-                to_regs.regs()[0],
-            ));
-            ret.push(Inst::imm(
-                OperandSize::Size64,
-                (value >> 64) as u64,
-                to_regs.regs()[1],
-            ));
+            let lo = value as u64;
+            let hi = (value >> 64) as u64;
+            let lo_reg = to_regs.regs()[0];
+            let hi_reg = to_regs.regs()[1];
+            if lo == 0 {
+                ret.push(Inst::alu_rmi_r(
+                    OperandSize::Size64,
+                    AluRmiROpcode::Xor,
+                    RegMemImm::reg(lo_reg.to_reg()),
+                    lo_reg,
+                ));
+            } else {
+                ret.push(Inst::imm(OperandSize::Size64, lo, lo_reg));
+            }
+            if hi == 0 {
+                ret.push(Inst::alu_rmi_r(
+                    OperandSize::Size64,
+                    AluRmiROpcode::Xor,
+                    RegMemImm::reg(hi_reg.to_reg()),
+                    hi_reg,
+                ));
+            } else {
+                ret.push(Inst::imm(OperandSize::Size64, hi, hi_reg));
+            }
         } else {
             let to_reg = to_regs
                 .only_reg()
diff --git a/cranelift/filetests/filetests/isa/x64/i128.clif b/cranelift/filetests/filetests/isa/x64/i128.clif
index fb49847e92..5066404fe0 100644
--- a/cranelift/filetests/filetests/isa/x64/i128.clif
+++ b/cranelift/filetests/filetests/isa/x64/i128.clif
@@ -702,10 +702,10 @@ block2(v6: i128):
 ; nextln:  testb   $$1, %dl
 ; nextln:  jnz     label1; j label2
 ; check: Block 1:
-; check:   movl    $$0, %edi
-; nextln:  movl    $$0, %esi
+; check:   xorq    %rdi, %rdi
+; nextln:  xorq    %rsi, %rsi
 ; nextln:  movl    $$1, %ecx
-; nextln:  movl    $$0, %eax
+; nextln:  xorq    %rax, %rax
 ; nextln:  addq    %rcx, %rdi
 ; nextln:  adcq    %rax, %rsi
 ; nextln:  movq    %rdi, %rax
@@ -714,10 +714,10 @@ block2(v6: i128):
 ; nextln:  popq    %rbp
 ; nextln:  ret
 ; check: Block 2:
-; check:   movl    $$0, %edi
-; nextln:  movl    $$0, %esi
+; check:   xorq    %rdi, %rdi
+; nextln:  xorq    %rsi, %rsi
 ; nextln:  movl    $$2, %ecx
-; nextln:  movl    $$0, %eax
+; nextln:  xorq    %rax, %rax
 ; nextln:  addq    %rcx, %rdi
 ; nextln:  adcq    %rax, %rsi
 ; nextln:  movq    %rdi, %rax