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Print encodings as [R#10c] instead of [R/10c].

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The # is a more conventional prefix for hexadecimal, and when ISA
information is not available, there may be a decimal number in front
which would be confusing.

So prefer [1#10c] for the ISA-less encoding format. Here '1' is decimal
and '#10c' is hexadecimal.
This commit is contained in:
Jakob Stoklund Olesen
2016-09-21 16:57:08 -07:00
parent 4e09b48dd4
commit 2ec50203fb
3 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
cranelift/src/libcretonne/isa/encoding.rs
View File

@@ -50,7 +50,7 @@ impl Default for Encoding {
impl fmt::Display for Encoding { impl fmt::Display for Encoding {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
if self.is_legal() { if self.is_legal() {
write!(f, "#{}/{:02x}", self.recipe, self.bits) write!(f, "{}#{:02x}", self.recipe, self.bits)
} else { } else {
write!(f, "-") write!(f, "-")
} }
@@ -68,7 +68,7 @@ impl fmt::Display for DisplayEncoding {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
if self.encoding.is_legal() { if self.encoding.is_legal() {
write!(f, write!(f,
"{}/{:02x}", "{}#{:02x}",
self.recipe_names[self.encoding.recipe()], self.recipe_names[self.encoding.recipe()],
self.encoding.bits) self.encoding.bits)
} else { } else {

8
cranelift/src/libcretonne/isa/riscv/mod.rs
View File

@@ -97,7 +97,7 @@ mod tests {
}; };
// ADDI is I/0b00100 // ADDI is I/0b00100
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst64).unwrap()), "I/04"); assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst64).unwrap()), "I#04");
// Try to encode iadd_imm.i64 vx1, -10000. // Try to encode iadd_imm.i64 vx1, -10000.
let inst64_large = InstructionData::BinaryImm { let inst64_large = InstructionData::BinaryImm {
@@ -119,7 +119,7 @@ mod tests {
}; };
// ADDIW is I/0b00110 // ADDIW is I/0b00110
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32).unwrap()), "I/06"); assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32).unwrap()), "I#06");
} }
// Same as above, but for RV32. // Same as above, but for RV32.
@@ -166,7 +166,7 @@ mod tests {
}; };
// ADDI is I/0b00100 // ADDI is I/0b00100
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32).unwrap()), "I/04"); assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32).unwrap()), "I#04");
// Create an imul.i32 which is encodable in RV32, but only when use_m is true. // Create an imul.i32 which is encodable in RV32, but only when use_m is true.
let mul32 = InstructionData::Binary { let mul32 = InstructionData::Binary {
@@ -201,6 +201,6 @@ mod tests {
ty: types::I32, ty: types::I32,
args: [arg32, arg32], args: [arg32, arg32],
}; };
assert_eq!(encstr(&*isa, isa.encode(&dfg, &mul32).unwrap()), "R/10c"); assert_eq!(encstr(&*isa, isa.encode(&dfg, &mul32).unwrap()), "R#10c");
} }
} }

2
meta/cretonne/__init__.py
View File

@@ -1205,7 +1205,7 @@ class Encoding(object):
self.isap = And.combine(recipe.isap, isap) self.isap = And.combine(recipe.isap, isap)
def __str__(self): def __str__(self):
return '[{}/{:02x}]'.format(self.recipe, self.encbits) return '[{}#{:02x}]'.format(self.recipe, self.encbits)
def ctrl_typevar(self): def ctrl_typevar(self):
""" """