diff --git a/cranelift/src/libcretonne/isa/encoding.rs b/cranelift/src/libcretonne/isa/encoding.rs
index 0bb1f6cc62..4c8e33a764 100644
--- a/cranelift/src/libcretonne/isa/encoding.rs
+++ b/cranelift/src/libcretonne/isa/encoding.rs
@@ -50,7 +50,7 @@ impl Default for Encoding {
 impl fmt::Display for Encoding {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         if self.is_legal() {
-            write!(f, "#{}/{:02x}", self.recipe, self.bits)
+            write!(f, "{}#{:02x}", self.recipe, self.bits)
         } else {
             write!(f, "-")
         }
@@ -68,7 +68,7 @@ impl fmt::Display for DisplayEncoding {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         if self.encoding.is_legal() {
             write!(f,
-                   "{}/{:02x}",
+                   "{}#{:02x}",
                    self.recipe_names[self.encoding.recipe()],
                    self.encoding.bits)
         } else {
diff --git a/cranelift/src/libcretonne/isa/riscv/mod.rs b/cranelift/src/libcretonne/isa/riscv/mod.rs
index 2ff352918d..cdc49f6973 100644
--- a/cranelift/src/libcretonne/isa/riscv/mod.rs
+++ b/cranelift/src/libcretonne/isa/riscv/mod.rs
@@ -97,7 +97,7 @@ mod tests {
         };
 
         // ADDI is I/0b00100
-        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst64).unwrap()), "I/04");
+        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst64).unwrap()), "I#04");
 
         // Try to encode iadd_imm.i64 vx1, -10000.
         let inst64_large = InstructionData::BinaryImm {
@@ -119,7 +119,7 @@ mod tests {
         };
 
         // ADDIW is I/0b00110
-        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32).unwrap()), "I/06");
+        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32).unwrap()), "I#06");
     }
 
     // Same as above, but for RV32.
@@ -166,7 +166,7 @@ mod tests {
         };
 
         // ADDI is I/0b00100
-        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32).unwrap()), "I/04");
+        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32).unwrap()), "I#04");
 
         // Create an imul.i32 which is encodable in RV32, but only when use_m is true.
         let mul32 = InstructionData::Binary {
@@ -201,6 +201,6 @@ mod tests {
             ty: types::I32,
             args: [arg32, arg32],
         };
-        assert_eq!(encstr(&*isa, isa.encode(&dfg, &mul32).unwrap()), "R/10c");
+        assert_eq!(encstr(&*isa, isa.encode(&dfg, &mul32).unwrap()), "R#10c");
     }
 }
diff --git a/meta/cretonne/__init__.py b/meta/cretonne/__init__.py
index 82b0a02be6..90cbb2f983 100644
--- a/meta/cretonne/__init__.py
+++ b/meta/cretonne/__init__.py
@@ -1205,7 +1205,7 @@ class Encoding(object):
         self.isap = And.combine(recipe.isap, isap)
 
     def __str__(self):
-        return '[{}/{:02x}]'.format(self.recipe, self.encbits)
+        return '[{}#{:02x}]'.format(self.recipe, self.encbits)
 
     def ctrl_typevar(self):
         """