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Add packed integer add opcodes (v128) to instruction set enum

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Johnnie Birch
2020-08-05 09:37:52 -07:00
parent b5a6daedc4
commit 2eadc6e2a8
3 changed files with 18 additions and 0 deletions
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12
cranelift/codegen/src/isa/x64/inst/args.rs
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@@ -391,6 +391,10 @@ pub enum SseOpcode {
Mulsd, Mulsd,
Orps, Orps,
Orpd, Orpd,
Paddb,
Paddd,
Paddq,
Paddw,
Psllw, Psllw,
Pslld, Pslld,
Psllq, Psllq,
@@ -479,6 +483,10 @@ impl SseOpcode {
| SseOpcode::Mulpd | SseOpcode::Mulpd
| SseOpcode::Mulsd | SseOpcode::Mulsd
| SseOpcode::Orpd | SseOpcode::Orpd
| SseOpcode::Paddb
| SseOpcode::Paddd
| SseOpcode::Paddq
| SseOpcode::Paddw
| SseOpcode::Psllw | SseOpcode::Psllw
| SseOpcode::Pslld | SseOpcode::Pslld
| SseOpcode::Psllq | SseOpcode::Psllq
@@ -559,6 +567,10 @@ impl fmt::Debug for SseOpcode {
SseOpcode::Mulsd => "mulsd", SseOpcode::Mulsd => "mulsd",
SseOpcode::Orpd => "orpd", SseOpcode::Orpd => "orpd",
SseOpcode::Orps => "orps", SseOpcode::Orps => "orps",
SseOpcode::Paddb => "paddb",
SseOpcode::Paddd => "paddd",
SseOpcode::Paddq => "paddq",
SseOpcode::Paddw => "paddw",
SseOpcode::Psllw => "psllw", SseOpcode::Psllw => "psllw",
SseOpcode::Pslld => "pslld", SseOpcode::Pslld => "pslld",
SseOpcode::Psllq => "psllq", SseOpcode::Psllq => "psllq",

4
cranelift/codegen/src/isa/x64/inst/emit.rs
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@@ -1659,6 +1659,10 @@ pub(crate) fn emit(
SseOpcode::Mulsd => (LegacyPrefix::_F2, 0x0F59), SseOpcode::Mulsd => (LegacyPrefix::_F2, 0x0F59),
SseOpcode::Orpd => (LegacyPrefix::_66, 0x0F56), SseOpcode::Orpd => (LegacyPrefix::_66, 0x0F56),
SseOpcode::Orps => (LegacyPrefix::None, 0x0F56), SseOpcode::Orps => (LegacyPrefix::None, 0x0F56),
SseOpcode::Paddb => (LegacyPrefix::_66, 0x0FFC),
SseOpcode::Paddd => (LegacyPrefix::_66, 0x0FFE),
SseOpcode::Paddq => (LegacyPrefix::_66, 0x0FD4),
SSeOpcode::Paddw => (LegacyPrefix::_66, 0x0FFD),
SseOpcode::Subps => (LegacyPrefix::None, 0x0F5C), SseOpcode::Subps => (LegacyPrefix::None, 0x0F5C),
SseOpcode::Subpd => (LegacyPrefix::_66, 0x0F5C), SseOpcode::Subpd => (LegacyPrefix::_66, 0x0F5C),
SseOpcode::Subss => (LegacyPrefix::_F3, 0x0F5C), SseOpcode::Subss => (LegacyPrefix::_F3, 0x0F5C),

2
cranelift/codegen/src/isa/x64/lower.rs
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@@ -349,10 +349,12 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
let lhs = input_to_reg(ctx, inputs[0]); let lhs = input_to_reg(ctx, inputs[0]);
let rhs = input_to_reg_mem_imm(ctx, inputs[1]); let rhs = input_to_reg_mem_imm(ctx, inputs[1]);
let dst = output_to_reg(ctx, outputs[0]); let dst = output_to_reg(ctx, outputs[0]);
let ty = ty.unwrap();
// TODO For commutative operations (add, mul, and, or, xor), try to commute the // TODO For commutative operations (add, mul, and, or, xor), try to commute the
// operands if one is an immediate. // operands if one is an immediate.
println!("Type: {}", ty);
let is_64 = int_ty_is_64(ty.unwrap()); let is_64 = int_ty_is_64(ty.unwrap());
let alu_op = match op { let alu_op = match op {
Opcode::Iadd | Opcode::IaddIfcout => AluRmiROpcode::Add, Opcode::Iadd | Opcode::IaddIfcout => AluRmiROpcode::Add,