From 2eadc6e2a8b2ba1e56182b927dfe8e96adac6479 Mon Sep 17 00:00:00 2001
From: Johnnie Birch <45402135+jlb6740@users.noreply.github.com>
Date: Wed, 5 Aug 2020 09:37:52 -0700
Subject: [PATCH] Add packed integer add opcodes (v128) to instruction set enum

---
 cranelift/codegen/src/isa/x64/inst/args.rs | 12 ++++++++++++
 cranelift/codegen/src/isa/x64/inst/emit.rs |  4 ++++
 cranelift/codegen/src/isa/x64/lower.rs     |  2 ++
 3 files changed, 18 insertions(+)

diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs
index 7cd6a2caef..100aefe2d5 100644
--- a/cranelift/codegen/src/isa/x64/inst/args.rs
+++ b/cranelift/codegen/src/isa/x64/inst/args.rs
@@ -391,6 +391,10 @@ pub enum SseOpcode {
     Mulsd,
     Orps,
     Orpd,
+    Paddb,
+    Paddd,
+    Paddq,
+    Paddw,
     Psllw,
     Pslld,
     Psllq,
@@ -479,6 +483,10 @@ impl SseOpcode {
             | SseOpcode::Mulpd
             | SseOpcode::Mulsd
             | SseOpcode::Orpd
+            | SseOpcode::Paddb
+            | SseOpcode::Paddd
+            | SseOpcode::Paddq
+            | SseOpcode::Paddw
             | SseOpcode::Psllw
             | SseOpcode::Pslld
             | SseOpcode::Psllq
@@ -559,6 +567,10 @@ impl fmt::Debug for SseOpcode {
             SseOpcode::Mulsd => "mulsd",
             SseOpcode::Orpd => "orpd",
             SseOpcode::Orps => "orps",
+            SseOpcode::Paddb => "paddb",
+            SseOpcode::Paddd => "paddd",
+            SseOpcode::Paddq => "paddq",
+            SseOpcode::Paddw => "paddw",
             SseOpcode::Psllw => "psllw",
             SseOpcode::Pslld => "pslld",
             SseOpcode::Psllq => "psllq",
diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs
index 1aa5b1b1a7..22c20cc241 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit.rs
@@ -1659,6 +1659,10 @@ pub(crate) fn emit(
                 SseOpcode::Mulsd => (LegacyPrefix::_F2, 0x0F59),
                 SseOpcode::Orpd => (LegacyPrefix::_66, 0x0F56),
                 SseOpcode::Orps => (LegacyPrefix::None, 0x0F56),
+                SseOpcode::Paddb => (LegacyPrefix::_66, 0x0FFC),
+                SseOpcode::Paddd => (LegacyPrefix::_66, 0x0FFE),
+                SseOpcode::Paddq => (LegacyPrefix::_66, 0x0FD4),
+                SSeOpcode::Paddw => (LegacyPrefix::_66, 0x0FFD),
                 SseOpcode::Subps => (LegacyPrefix::None, 0x0F5C),
                 SseOpcode::Subpd => (LegacyPrefix::_66, 0x0F5C),
                 SseOpcode::Subss => (LegacyPrefix::_F3, 0x0F5C),
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index acc261f3c1..ac58b2b2a0 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -349,10 +349,12 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             let lhs = input_to_reg(ctx, inputs[0]);
             let rhs = input_to_reg_mem_imm(ctx, inputs[1]);
             let dst = output_to_reg(ctx, outputs[0]);
+            let ty = ty.unwrap();
 
             // TODO For commutative operations (add, mul, and, or, xor), try to commute the
             // operands if one is an immediate.
 
+            println!("Type: {}", ty);
             let is_64 = int_ty_is_64(ty.unwrap());
             let alu_op = match op {
                 Opcode::Iadd | Opcode::IaddIfcout => AluRmiROpcode::Add,