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aarch64: Add ands instruction encoding

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This commit is contained in:
Afonso Bordado
2021-06-08 10:51:57 +01:00
parent c38a5e8b62
commit 2c4d1c0003
3 changed files with 78 additions and 0 deletions
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4
cranelift/codegen/src/isa/aarch64/inst/mod.rs
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@@ -52,6 +52,8 @@ pub enum ALUOp {
OrrNot64,
And32,
And64,
AndS32,
AndS64,
AndNot32,
AndNot64,
/// XOR (AArch64 calls this "EOR")
@@ -3186,6 +3188,8 @@ impl Inst {
ALUOp::Orr64 => ("orr", OperandSize::Size64),
ALUOp::And32 => ("and", OperandSize::Size32),
ALUOp::And64 => ("and", OperandSize::Size64),
ALUOp::AndS32 => ("ands", OperandSize::Size32),
ALUOp::AndS64 => ("ands", OperandSize::Size64),
ALUOp::Eor32 => ("eor", OperandSize::Size32),
ALUOp::Eor64 => ("eor", OperandSize::Size64),
ALUOp::AddS32 => ("adds", OperandSize::Size32),