From 2c4d1c0003954778e49f3e9dd3ec0cafc9d5c8dd Mon Sep 17 00:00:00 2001
From: Afonso Bordado <afonsobordado@az8.co>
Date: Tue, 8 Jun 2021 10:51:57 +0100
Subject: [PATCH] aarch64: Add ands instruction encoding

---
 .../codegen/src/isa/aarch64/inst/emit.rs      |  6 ++
 .../src/isa/aarch64/inst/emit_tests.rs        | 68 +++++++++++++++++++
 cranelift/codegen/src/isa/aarch64/inst/mod.rs |  4 ++
 3 files changed, 78 insertions(+)

diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
index 60fedcd0d3..02027d48d4 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -607,6 +607,8 @@ impl MachInstEmit for Inst {
                     ALUOp::Orr64 => 0b10101010_000,
                     ALUOp::And32 => 0b00001010_000,
                     ALUOp::And64 => 0b10001010_000,
+                    ALUOp::AndS32 => 0b01101010_000,
+                    ALUOp::AndS64 => 0b11101010_000,
                     ALUOp::Eor32 => 0b01001010_000,
                     ALUOp::Eor64 => 0b11001010_000,
                     ALUOp::OrrNot32 => 0b00101010_001,
@@ -694,6 +696,8 @@ impl MachInstEmit for Inst {
                     ALUOp::Orr64 => (0b101_100100, false),
                     ALUOp::And32 => (0b000_100100, false),
                     ALUOp::And64 => (0b100_100100, false),
+                    ALUOp::AndS32 => (0b011_100100, false),
+                    ALUOp::AndS64 => (0b111_100100, false),
                     ALUOp::Eor32 => (0b010_100100, false),
                     ALUOp::Eor64 => (0b110_100100, false),
                     ALUOp::OrrNot32 => (0b001_100100, true),
@@ -763,6 +767,8 @@ impl MachInstEmit for Inst {
                     ALUOp::Orr64 => 0b101_01010000,
                     ALUOp::And32 => 0b000_01010000,
                     ALUOp::And64 => 0b100_01010000,
+                    ALUOp::AndS32 => 0b011_01010000,
+                    ALUOp::AndS64 => 0b111_01010000,
                     ALUOp::Eor32 => 0b010_01010000,
                     ALUOp::Eor64 => 0b110_01010000,
                     ALUOp::OrrNot32 => 0b001_01010001,
diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
index 530269b201..b6fa2125ce 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
@@ -151,6 +151,26 @@ fn test_aarch64_binemit() {
         "A400068A",
         "and x4, x5, x6",
     ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::AndS32,
+            rd: writable_xreg(1),
+            rn: xreg(2),
+            rm: xreg(3),
+        },
+        "4100036A",
+        "ands w1, w2, w3",
+    ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::AndS64,
+            rd: writable_xreg(4),
+            rn: xreg(5),
+            rm: xreg(6),
+        },
+        "A40006EA",
+        "ands x4, x5, x6",
+    ));
     insns.push((
         Inst::AluRRR {
             alu_op: ALUOp::SubS32,
@@ -648,6 +668,34 @@ fn test_aarch64_binemit() {
         "6A5D0C8A",
         "and x10, x11, x12, LSL 23",
     ));
+    insns.push((
+        Inst::AluRRRShift {
+            alu_op: ALUOp::AndS32,
+            rd: writable_xreg(10),
+            rn: xreg(11),
+            rm: xreg(12),
+            shiftop: ShiftOpAndAmt::new(
+                ShiftOp::LSL,
+                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
+            ),
+        },
+        "6A5D0C6A",
+        "ands w10, w11, w12, LSL 23",
+    ));
+    insns.push((
+        Inst::AluRRRShift {
+            alu_op: ALUOp::AndS64,
+            rd: writable_xreg(10),
+            rn: xreg(11),
+            rm: xreg(12),
+            shiftop: ShiftOpAndAmt::new(
+                ShiftOp::LSL,
+                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
+            ),
+        },
+        "6A5D0CEA",
+        "ands x10, x11, x12, LSL 23",
+    ));
     insns.push((
         Inst::AluRRRShift {
             alu_op: ALUOp::Eor32,
@@ -1015,6 +1063,26 @@ fn test_aarch64_binemit() {
         "C7381592",
         "and x7, x6, #288221580125796352",
     ));
+    insns.push((
+        Inst::AluRRImmLogic {
+            alu_op: ALUOp::AndS32,
+            rd: writable_xreg(21),
+            rn: xreg(27),
+            imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
+        },
+        "753B0172",
+        "ands w21, w27, #2147500031",
+    ));
+    insns.push((
+        Inst::AluRRImmLogic {
+            alu_op: ALUOp::AndS64,
+            rd: writable_xreg(7),
+            rn: xreg(6),
+            imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
+        },
+        "C73815F2",
+        "ands x7, x6, #288221580125796352",
+    ));
     insns.push((
         Inst::AluRRImmLogic {
             alu_op: ALUOp::Orr32,
diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
index ecdf43c6ff..07cac9483b 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -52,6 +52,8 @@ pub enum ALUOp {
     OrrNot64,
     And32,
     And64,
+    AndS32,
+    AndS64,
     AndNot32,
     AndNot64,
     /// XOR (AArch64 calls this "EOR")
@@ -3186,6 +3188,8 @@ impl Inst {
                 ALUOp::Orr64 => ("orr", OperandSize::Size64),
                 ALUOp::And32 => ("and", OperandSize::Size32),
                 ALUOp::And64 => ("and", OperandSize::Size64),
+                ALUOp::AndS32 => ("ands", OperandSize::Size32),
+                ALUOp::AndS64 => ("ands", OperandSize::Size64),
                 ALUOp::Eor32 => ("eor", OperandSize::Size32),
                 ALUOp::Eor64 => ("eor", OperandSize::Size64),
                 ALUOp::AddS32 => ("adds", OperandSize::Size32),