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aarch64: Add ands instruction encoding

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This commit is contained in:
Afonso Bordado
2021-06-08 10:51:57 +01:00
parent c38a5e8b62
commit 2c4d1c0003
3 changed files with 78 additions and 0 deletions
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68
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
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@@ -151,6 +151,26 @@ fn test_aarch64_binemit() {
"A400068A",
"and x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndS32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100036A",
"ands w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndS64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006EA",
"ands x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubS32,
@@ -648,6 +668,34 @@ fn test_aarch64_binemit() {
"6A5D0C8A",
"and x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndS32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0C6A",
"ands w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndS64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0CEA",
"ands x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Eor32,
@@ -1015,6 +1063,26 @@ fn test_aarch64_binemit() {
"C7381592",
"and x7, x6, #288221580125796352",
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::AndS32,
rd: writable_xreg(21),
rn: xreg(27),
imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
},
"753B0172",
"ands w21, w27, #2147500031",
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::AndS64,
rd: writable_xreg(7),
rn: xreg(6),
imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
},
"C73815F2",
"ands x7, x6, #288221580125796352",
));
insns.push((
Inst::AluRRImmLogic {
alu_op: ALUOp::Orr32,