CL/aarch64 back end: implement the wasm SIMD bitmask instructions
The `bitmask.{8x16,16x8,32x4}` instructions do not map neatly to any single
AArch64 SIMD instruction, and instead need a sequence of around ten
instructions. Because of this, this patch is somewhat longer and more complex
than it would be for (eg) x64.
Main changes are:
* the relevant testsuite test (`simd_boolean.wast`) has been enabled on aarch64.
* at the CLIF level, add a new instruction `vhigh_bits`, into which these wasm
instructions are to be translated.
* in the wasm->CLIF translation (code_translator.rs), translate into
`vhigh_bits`. This is straightforward.
* in the CLIF->AArch64 translation (lower_inst.rs), translate `vhigh_bits`
into equivalent sequences of AArch64 instructions. There is a different
sequence for each of the `{8x16, 16x8, 32x4}` variants.
All other changes are AArch64-specific, and add instruction definitions needed
by the previous step:
* Add two new families of AArch64 instructions: `VecShiftImm` (vector shift by
immediate) and `VecExtract` (effectively a double-length vector shift)
* To the existing AArch64 family `VecRRR`, add a `zip1` variant. To the
`VecLanesOp` family add an `addv` variant.
* Add supporting code for the above changes to AArch64 instructions:
- getting the register uses (`aarch64_get_regs`)
- mapping the registers (`aarch64_map_regs`)
- printing instructions
- emitting instructions (`impl MachInstEmit for Inst`). The handling of
`VecShiftImm` is a bit complex.
- emission tests for new instructions and variants.
This commit is contained in:
Julian Seward
committed by
julian-seward1
julian-seward1
parent
b10e027fef
commit
2702942050
@@ -2060,6 +2060,197 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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normalize_bool_result(ctx, insn, rd);
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}
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Opcode::VhighBits => {
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let dst_r = get_output_reg(ctx, outputs[0]);
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let src_v = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
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let ty = ctx.input_ty(insn, 0);
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// All three sequences use one integer temporary and two vector temporaries. The
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// shift is done early so as to give the register allocator the possibility of using
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// the same reg for `tmp_v1` and `src_v` in the case that this is the last use of
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// `src_v`. See https://github.com/WebAssembly/simd/pull/201 for the background and
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// derivation of these sequences. Alternative sequences are discussed in
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// https://github.com/bytecodealliance/wasmtime/issues/2296, although they are not
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// used here.
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// Also .. FIXME: when https://github.com/bytecodealliance/wasmtime/pull/2310 is
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// merged, use `lower_splat_constant` instead to generate the constants.
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let tmp_r0 = ctx.alloc_tmp(RegClass::I64, I64);
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let tmp_v0 = ctx.alloc_tmp(RegClass::V128, I8X16);
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let tmp_v1 = ctx.alloc_tmp(RegClass::V128, I8X16);
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match ty {
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I8X16 => {
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// sshr tmp_v1.16b, src_v.16b, #7
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// mov tmp_r0, #0x0201
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// movk tmp_r0, #0x0804, lsl 16
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// movk tmp_r0, #0x2010, lsl 32
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// movk tmp_r0, #0x8040, lsl 48
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// dup tmp_v0.2d, tmp_r0
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// and tmp_v1.16b, tmp_v1.16b, tmp_v0.16b
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// ext tmp_v0.16b, tmp_v1.16b, tmp_v1.16b, #8
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// zip1 tmp_v0.16b, tmp_v1.16b, tmp_v0.16b
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// addv tmp_v0h, tmp_v0.8h
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// mov dst_r, tmp_v0.h[0]
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ctx.emit(Inst::VecShiftImm {
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op: VecShiftImmOp::Sshr,
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rd: tmp_v1,
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rn: src_v,
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size: VectorSize::Size8x16,
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imm: 7,
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});
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lower_constant_u64(ctx, tmp_r0, 0x8040201008040201u64);
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ctx.emit(Inst::VecDup {
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rd: tmp_v0,
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rn: tmp_r0.to_reg(),
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size: VectorSize::Size64x2,
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});
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ctx.emit(Inst::VecRRR {
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alu_op: VecALUOp::And,
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rd: tmp_v1,
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rn: tmp_v1.to_reg(),
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rm: tmp_v0.to_reg(),
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size: VectorSize::Size8x16,
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});
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ctx.emit(Inst::VecExtract {
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rd: tmp_v0,
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rn: tmp_v1.to_reg(),
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rm: tmp_v1.to_reg(),
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imm4: 8,
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});
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ctx.emit(Inst::VecRRR {
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alu_op: VecALUOp::Zip1,
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rd: tmp_v0,
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rn: tmp_v1.to_reg(),
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rm: tmp_v0.to_reg(),
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size: VectorSize::Size8x16,
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});
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ctx.emit(Inst::VecLanes {
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op: VecLanesOp::Addv,
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rd: tmp_v0,
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rn: tmp_v0.to_reg(),
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size: VectorSize::Size16x8,
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});
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ctx.emit(Inst::MovFromVec {
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rd: dst_r,
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rn: tmp_v0.to_reg(),
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idx: 0,
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size: VectorSize::Size16x8,
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});
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}
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I16X8 => {
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// sshr tmp_v1.8h, src_v.8h, #15
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// mov tmp_r0, #0x1
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// movk tmp_r0, #0x2, lsl 16
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// movk tmp_r0, #0x4, lsl 32
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// movk tmp_r0, #0x8, lsl 48
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// dup tmp_v0.2d, tmp_r0
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// shl tmp_r0, tmp_r0, #4
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// mov tmp_v0.d[1], tmp_r0
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// and tmp_v0.16b, tmp_v1.16b, tmp_v0.16b
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// addv tmp_v0h, tmp_v0.8h
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// mov dst_r, tmp_v0.h[0]
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ctx.emit(Inst::VecShiftImm {
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op: VecShiftImmOp::Sshr,
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rd: tmp_v1,
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rn: src_v,
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size: VectorSize::Size16x8,
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imm: 15,
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});
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lower_constant_u64(ctx, tmp_r0, 0x0008000400020001u64);
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ctx.emit(Inst::VecDup {
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rd: tmp_v0,
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rn: tmp_r0.to_reg(),
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size: VectorSize::Size64x2,
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});
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ctx.emit(Inst::AluRRImmShift {
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alu_op: ALUOp::Lsl64,
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rd: tmp_r0,
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rn: tmp_r0.to_reg(),
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immshift: ImmShift { imm: 4 },
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});
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ctx.emit(Inst::MovToVec {
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rd: tmp_v0,
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rn: tmp_r0.to_reg(),
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idx: 1,
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size: VectorSize::Size64x2,
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});
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ctx.emit(Inst::VecRRR {
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alu_op: VecALUOp::And,
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rd: tmp_v0,
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rn: tmp_v1.to_reg(),
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rm: tmp_v0.to_reg(),
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size: VectorSize::Size8x16,
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});
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ctx.emit(Inst::VecLanes {
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op: VecLanesOp::Addv,
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rd: tmp_v0,
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rn: tmp_v0.to_reg(),
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size: VectorSize::Size16x8,
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});
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ctx.emit(Inst::MovFromVec {
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rd: dst_r,
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rn: tmp_v0.to_reg(),
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idx: 0,
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size: VectorSize::Size16x8,
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});
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}
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I32X4 => {
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// sshr tmp_v1.4s, src_v.4s, #31
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// mov tmp_r0, #0x1
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// movk tmp_r0, #0x2, lsl 32
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// dup tmp_v0.2d, tmp_r0
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// shl tmp_r0, tmp_r0, #2
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// mov tmp_v0.d[1], tmp_r0
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// and tmp_v0.16b, tmp_v1.16b, tmp_v0.16b
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// addv tmp_v0s, tmp_v0.4s
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// mov dst_r, tmp_v0.s[0]
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ctx.emit(Inst::VecShiftImm {
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op: VecShiftImmOp::Sshr,
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rd: tmp_v1,
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rn: src_v,
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size: VectorSize::Size32x4,
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imm: 31,
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});
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lower_constant_u64(ctx, tmp_r0, 0x0000000200000001u64);
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ctx.emit(Inst::VecDup {
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rd: tmp_v0,
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rn: tmp_r0.to_reg(),
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size: VectorSize::Size64x2,
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});
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ctx.emit(Inst::AluRRImmShift {
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alu_op: ALUOp::Lsl64,
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rd: tmp_r0,
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rn: tmp_r0.to_reg(),
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immshift: ImmShift { imm: 2 },
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});
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ctx.emit(Inst::MovToVec {
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rd: tmp_v0,
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rn: tmp_r0.to_reg(),
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idx: 1,
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size: VectorSize::Size64x2,
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});
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ctx.emit(Inst::VecRRR {
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alu_op: VecALUOp::And,
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rd: tmp_v0,
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rn: tmp_v1.to_reg(),
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rm: tmp_v0.to_reg(),
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size: VectorSize::Size8x16,
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});
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ctx.emit(Inst::VecLanes {
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op: VecLanesOp::Addv,
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rd: tmp_v0,
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rn: tmp_v0.to_reg(),
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size: VectorSize::Size32x4,
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});
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ctx.emit(Inst::MovFromVec {
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rd: dst_r,
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rn: tmp_v0.to_reg(),
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idx: 0,
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size: VectorSize::Size32x4,
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});
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}
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_ => panic!("arm64 isel: VhighBits unhandled, ty = {:?}", ty),
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}
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}
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Opcode::Shuffle => {
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let mask = const_param_to_u128(ctx, insn).expect("Invalid immediate mask bytes");
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let rd = get_output_reg(ctx, outputs[0]);
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