Cranelift: aarch64: fix undefined dest reg in f32x4.splat case. (#5987)

One of the cases for a splat operation, as updated in #5370, wrote to
a temp reg but then only conditionally transformed the temp into the
final destination register. In another codepath, `rd` was left
undefined. This causes a panic later when regalloc2 verifies SSA
properties of its input (here, value not def'd before use).

Fixes #5985.

cranelift/filetests/filetests/isa/aarch64/issue-5985.clif

@@ -0,0 +1,20 @@
+test compile precise-output
+target aarch64
+
+function %a() -> f32x4 system_v {
+block0:
+    v16 = f32const 0x1.fffe00p-126
+    v25 = splat.f32x4 v16
+    return v25
+}
+
+; VCode:
+; block0:
+;   movi v0.2d, #72056494543077120
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   movi v0.2d, #0xffff0000ffff00
+;   ret
+