264089e29d
One of the cases for a splat operation, as updated in #5370, wrote to a temp reg but then only conditionally transformed the temp into the final destination register. In another codepath, `rd` was left undefined. This causes a panic later when regalloc2 verifies SSA properties of its input (here, value not def'd before use). Fixes #5985.
21 lines
312 B
Plaintext
21 lines
312 B
Plaintext
test compile precise-output
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target aarch64
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function %a() -> f32x4 system_v {
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block0:
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v16 = f32const 0x1.fffe00p-126
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v25 = splat.f32x4 v16
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return v25
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}
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; VCode:
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; block0:
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; movi v0.2d, #72056494543077120
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; movi v0.2d, #0xffff0000ffff00
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; ret
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