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Support legalizing bconst instructions on x86.

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This commit is contained in:
Dan Gohman
2018-03-28 14:11:16 -07:00
parent c3f044ff46
commit 23ab07b54e
4 changed files with 24 additions and 1 deletions
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3
cranelift/filetests/isa/intel/binary32.cton
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@@ -25,6 +25,9 @@ ebb0:
; asm: movl $2, %esi ; asm: movl $2, %esi
[-,%rsi] v2 = iconst.i32 2 ; bin: be 00000002 [-,%rsi] v2 = iconst.i32 2 ; bin: be 00000002
; asm: movb $1, %cl
[-,%rcx] v9007 = bconst.b1 true ; bin: b9 00000001
; Integer Register-Register Operations. ; Integer Register-Register Operations.
; asm: addl %esi, %ecx ; asm: addl %esi, %ecx

5
cranelift/filetests/isa/intel/binary64.cton
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@@ -38,6 +38,11 @@ ebb0:
; asm: movq $0xffffffff88001122, %r14 # 32-bit sign-extended constant. ; asm: movq $0xffffffff88001122, %r14 # 32-bit sign-extended constant.
[-,%r14] v5 = iconst.i64 0xffff_ffff_8800_1122 ; bin: 49 c7 c6 88001122 [-,%r14] v5 = iconst.i64 0xffff_ffff_8800_1122 ; bin: 49 c7 c6 88001122
; asm: movb $1, %cl
[-,%rcx] v9007 = bconst.b1 true ; bin: b9 00000001
; asm: movb $1, %sil
[-,%r10] v9008 = bconst.b1 true ; bin: 41 ba 00000001
; Integer Register-Register Operations. ; Integer Register-Register Operations.
; asm: addq %rsi, %rcx ; asm: addq %rsi, %rcx

3
lib/cretonne/meta/isa/intel/encodings.py
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@@ -155,6 +155,9 @@ X86_64.enc(base.iconst.i64, *r.uid.rex(0xc7, rrr=0, w=1))
# Finally, the 0xb8 opcode takes an 8-byte immediate with a REX.W prefix. # Finally, the 0xb8 opcode takes an 8-byte immediate with a REX.W prefix.
X86_64.enc(base.iconst.i64, *r.puiq.rex(0xb8, w=1)) X86_64.enc(base.iconst.i64, *r.puiq.rex(0xb8, w=1))
# bool constants.
enc_both(base.bconst.b1, r.puid_bool, 0xb8)
# Shifts and rotates. # Shifts and rotates.
# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit # Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
# and 16-bit shifts would need explicit masking. # and 16-bit shifts would need explicit masking.

14
lib/cretonne/meta/isa/intel/recipes.py
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@@ -5,7 +5,8 @@ from __future__ import absolute_import
from cdsl.isa import EncRecipe from cdsl.isa import EncRecipe
from cdsl.predicates import IsSignedInt, IsEqual, Or from cdsl.predicates import IsSignedInt, IsEqual, Or
from cdsl.registers import RegClass from cdsl.registers import RegClass
from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry, NullAry from base.formats import Unary, UnaryImm, UnaryBool, Binary, BinaryImm
from base.formats import MultiAry, NullAry
from base.formats import Trap, Call, IndirectCall, Store, Load from base.formats import Trap, Call, IndirectCall, Store, Load
from base.formats import IntCompare, FloatCompare, IntCond, FloatCond from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
from base.formats import IntSelect, IntCondTrap, FloatCondTrap from base.formats import IntSelect, IntCondTrap, FloatCondTrap
@@ -506,6 +507,17 @@ puid = TailRecipe(
sink.put4(imm as u32); sink.put4(imm as u32);
''') ''')
# XX+rd id unary with bool immediate. Note no recipe predicate.
puid_bool = TailRecipe(
'puid_bool', UnaryBool, size=4, ins=(), outs=GPR,
emit='''
// The destination register is encoded in the low bits of the opcode.
// No ModR/M.
PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
let imm: u32 = if imm.into() { 1 } else { 0 };
sink.put4(imm);
''')
# XX+rd iq unary with 64-bit immediate. # XX+rd iq unary with 64-bit immediate.
puiq = TailRecipe( puiq = TailRecipe(
'puiq', UnaryImm, size=8, ins=(), outs=GPR, 'puiq', UnaryImm, size=8, ins=(), outs=GPR,