diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index 771bb19af2..04f492c354 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -25,6 +25,9 @@ ebb0:
     ; asm: movl $2, %esi
     [-,%rsi]            v2 = iconst.i32 2        ; bin: be 00000002
 
+    ; asm: movb $1, %cl
+    [-,%rcx]            v9007 = bconst.b1 true      ; bin: b9 00000001
+
     ; Integer Register-Register Operations.
 
     ; asm: addl %esi, %ecx
diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton
index 3c35bd2a0c..f7aab2f8f4 100644
--- a/cranelift/filetests/isa/intel/binary64.cton
+++ b/cranelift/filetests/isa/intel/binary64.cton
@@ -38,6 +38,11 @@ ebb0:
     ; asm: movq $0xffffffff88001122, %r14                     # 32-bit sign-extended constant.
     [-,%r14]            v5 = iconst.i64 0xffff_ffff_8800_1122 ; bin: 49 c7 c6 88001122
 
+    ; asm: movb $1, %cl
+    [-,%rcx]            v9007 = bconst.b1 true      ; bin: b9 00000001
+    ; asm: movb $1, %sil
+    [-,%r10]            v9008 = bconst.b1 true      ; bin: 41 ba 00000001
+
     ; Integer Register-Register Operations.
 
     ; asm: addq %rsi, %rcx
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index fca2ce8699..72ef7a362b 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -155,6 +155,9 @@ X86_64.enc(base.iconst.i64, *r.uid.rex(0xc7, rrr=0, w=1))
 # Finally, the 0xb8 opcode takes an 8-byte immediate with a REX.W prefix.
 X86_64.enc(base.iconst.i64, *r.puiq.rex(0xb8, w=1))
 
+# bool constants.
+enc_both(base.bconst.b1, r.puid_bool, 0xb8)
+
 # Shifts and rotates.
 # Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
 # and 16-bit shifts would need explicit masking.
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 5c37677f14..2406ef6ade 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -5,7 +5,8 @@ from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt, IsEqual, Or
 from cdsl.registers import RegClass
-from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry, NullAry
+from base.formats import Unary, UnaryImm, UnaryBool, Binary, BinaryImm
+from base.formats import MultiAry, NullAry
 from base.formats import Trap, Call, IndirectCall, Store, Load
 from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
 from base.formats import IntSelect, IntCondTrap, FloatCondTrap
@@ -506,6 +507,17 @@ puid = TailRecipe(
         sink.put4(imm as u32);
         ''')
 
+# XX+rd id unary with bool immediate. Note no recipe predicate.
+puid_bool = TailRecipe(
+        'puid_bool', UnaryBool, size=4, ins=(), outs=GPR,
+        emit='''
+        // The destination register is encoded in the low bits of the opcode.
+        // No ModR/M.
+        PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
+        let imm: u32 = if imm.into() { 1 } else { 0 };
+        sink.put4(imm);
+        ''')
+
 # XX+rd iq unary with 64-bit immediate.
 puiq = TailRecipe(
         'puiq', UnaryImm, size=8, ins=(), outs=GPR,