Support legalizing bconst instructions on x86.

lib/cretonne/meta/isa/intel/encodings.py

@@ -155,6 +155,9 @@ X86_64.enc(base.iconst.i64, *r.uid.rex(0xc7, rrr=0, w=1))
 # Finally, the 0xb8 opcode takes an 8-byte immediate with a REX.W prefix.
 X86_64.enc(base.iconst.i64, *r.puiq.rex(0xb8, w=1))
 
+# bool constants.
+enc_both(base.bconst.b1, r.puid_bool, 0xb8)
+
 # Shifts and rotates.
 # Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
 # and 16-bit shifts would need explicit masking.

lib/cretonne/meta/isa/intel/recipes.py

@@ -5,7 +5,8 @@ from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt, IsEqual, Or
 from cdsl.registers import RegClass
-from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry, NullAry
+from base.formats import Unary, UnaryImm, UnaryBool, Binary, BinaryImm
+from base.formats import MultiAry, NullAry
 from base.formats import Trap, Call, IndirectCall, Store, Load
 from base.formats import IntCompare, FloatCompare, IntCond, FloatCond
 from base.formats import IntSelect, IntCondTrap, FloatCondTrap
@@ -506,6 +507,17 @@ puid = TailRecipe(
         sink.put4(imm as u32);
         ''')
 
+# XX+rd id unary with bool immediate. Note no recipe predicate.
+puid_bool = TailRecipe(
+        'puid_bool', UnaryBool, size=4, ins=(), outs=GPR,
+        emit='''
+        // The destination register is encoded in the low bits of the opcode.
+        // No ModR/M.
+        PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
+        let imm: u32 = if imm.into() { 1 } else { 0 };
+        sink.put4(imm);
+        ''')
+
 # XX+rd iq unary with 64-bit immediate.
 puiq = TailRecipe(
         'puiq', UnaryImm, size=8, ins=(), outs=GPR,