Add operand register constraints.

Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.

lib/cretonne/src/isa/arm64/enc_tables.rs

@@ -4,5 +4,6 @@ use ir::InstructionData;
 use ir::instructions::InstructionFormat;
 use ir::types;
 use isa::enc_tables::{Level1Entry, Level2Entry};
+use isa::constraints::*;
 
 include!(concat!(env!("OUT_DIR"), "/encoding-arm64.rs"));

lib/cretonne/src/isa/arm64/mod.rs

@@ -7,7 +7,7 @@ mod registers;
 use super::super::settings as shared_settings;
 use isa::enc_tables::{lookup_enclist, general_encoding};
 use isa::Builder as IsaBuilder;
-use isa::{TargetIsa, RegInfo, Encoding, Legalize};
+use isa::{TargetIsa, RegInfo, Encoding, Legalize, RecipeConstraints};
 use ir::{InstructionData, DataFlowGraph};
 
 #[allow(dead_code)]
@@ -63,4 +63,8 @@ impl TargetIsa for Isa {
     fn recipe_names(&self) -> &'static [&'static str] {
         &enc_tables::RECIPE_NAMES[..]
     }
+
+    fn recipe_constraints(&self) -> &'static [RecipeConstraints] {
+        &enc_tables::RECIPE_CONSTRAINTS
+    }
 }