2390e3e3f0
Every encoding recipe must specify register constraints on input and output values. Generate recipe constraint tables along with the other encoding tables.
71 lines
2.0 KiB
Rust
71 lines
2.0 KiB
Rust
//! ARM 64-bit Instruction Set Architecture.
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pub mod settings;
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mod enc_tables;
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mod registers;
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use super::super::settings as shared_settings;
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use isa::enc_tables::{lookup_enclist, general_encoding};
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use isa::Builder as IsaBuilder;
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use isa::{TargetIsa, RegInfo, Encoding, Legalize, RecipeConstraints};
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use ir::{InstructionData, DataFlowGraph};
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#[allow(dead_code)]
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struct Isa {
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shared_flags: shared_settings::Flags,
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isa_flags: settings::Flags,
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}
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/// Get an ISA builder for creating ARM64 targets.
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pub fn isa_builder() -> IsaBuilder {
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IsaBuilder {
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setup: settings::builder(),
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constructor: isa_constructor,
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}
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}
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fn isa_constructor(shared_flags: shared_settings::Flags,
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builder: &shared_settings::Builder)
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-> Box<TargetIsa> {
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Box::new(Isa {
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isa_flags: settings::Flags::new(&shared_flags, builder),
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shared_flags: shared_flags,
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})
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}
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impl TargetIsa for Isa {
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fn name(&self) -> &'static str {
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"arm64"
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}
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fn flags(&self) -> &shared_settings::Flags {
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&self.shared_flags
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}
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fn register_info(&self) -> &RegInfo {
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®isters::INFO
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}
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fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
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lookup_enclist(inst.first_type(),
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inst.opcode(),
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&enc_tables::LEVEL1_A64[..],
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&enc_tables::LEVEL2[..])
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.and_then(|enclist_offset| {
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general_encoding(enclist_offset,
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&enc_tables::ENCLISTS[..],
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|instp| enc_tables::check_instp(inst, instp),
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|isap| self.isa_flags.numbered_predicate(isap as usize))
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.ok_or(Legalize::Expand)
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})
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}
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fn recipe_names(&self) -> &'static [&'static str] {
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&enc_tables::RECIPE_NAMES[..]
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}
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fn recipe_constraints(&self) -> &'static [RecipeConstraints] {
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&enc_tables::RECIPE_CONSTRAINTS
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}
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}
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