bextend/breduce need constraints
This commit is contained in:
committed by
Jakob Stoklund Olesen
parent
b04a2c30d2
commit
2387745847
@@ -1382,7 +1382,7 @@ breduce = Instruction(
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The result type must have the same number of vector lanes as the input,
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and each lane must not have more bits that the input lanes. If the
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input and output types are the same, this is a no-op.
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""", ins=x, outs=a)
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""", ins=x, outs=a, constraints=WiderOrEq(Bool, BoolTo))
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BoolTo = TypeVar(
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'BoolTo',
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@@ -1399,7 +1399,7 @@ bextend = Instruction(
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The result type must have the same number of vector lanes as the input,
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and each lane must not have fewer bits that the input lanes. If the
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input and output types are the same, this is a no-op.
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""", ins=x, outs=a)
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""", ins=x, outs=a, constraints=WiderOrEq(BoolTo, Bool))
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IntTo = TypeVar(
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'IntTo', 'An integer type with the same number of lanes',
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