From 23877458474ac26d62fc9ef8593b8187fb8b27cd Mon Sep 17 00:00:00 2001 From: Dimo Date: Wed, 26 Jul 2017 14:41:59 -0700 Subject: [PATCH] bextend/breduce need constraints --- lib/cretonne/meta/base/instructions.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/cretonne/meta/base/instructions.py b/lib/cretonne/meta/base/instructions.py index 763550a5ee..a26d791719 100644 --- a/lib/cretonne/meta/base/instructions.py +++ b/lib/cretonne/meta/base/instructions.py @@ -1382,7 +1382,7 @@ breduce = Instruction( The result type must have the same number of vector lanes as the input, and each lane must not have more bits that the input lanes. If the input and output types are the same, this is a no-op. - """, ins=x, outs=a) + """, ins=x, outs=a, constraints=WiderOrEq(Bool, BoolTo)) BoolTo = TypeVar( 'BoolTo', @@ -1399,7 +1399,7 @@ bextend = Instruction( The result type must have the same number of vector lanes as the input, and each lane must not have fewer bits that the input lanes. If the input and output types are the same, this is a no-op. - """, ins=x, outs=a) + """, ins=x, outs=a, constraints=WiderOrEq(BoolTo, Bool)) IntTo = TypeVar( 'IntTo', 'An integer type with the same number of lanes',