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bextend/breduce need constraints

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This commit is contained in:
Dimo
2017-07-26 14:41:59 -07:00
committed by Jakob Stoklund Olesen
parent b04a2c30d2
commit 2387745847
1 changed files with 2 additions and 2 deletions
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4
lib/cretonne/meta/base/instructions.py
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@@ -1382,7 +1382,7 @@ breduce = Instruction(
The result type must have the same number of vector lanes as the input, The result type must have the same number of vector lanes as the input,
and each lane must not have more bits that the input lanes. If the and each lane must not have more bits that the input lanes. If the
input and output types are the same, this is a no-op. input and output types are the same, this is a no-op.
""", ins=x, outs=a) """, ins=x, outs=a, constraints=WiderOrEq(Bool, BoolTo))
BoolTo = TypeVar( BoolTo = TypeVar(
'BoolTo', 'BoolTo',
@@ -1399,7 +1399,7 @@ bextend = Instruction(
The result type must have the same number of vector lanes as the input, The result type must have the same number of vector lanes as the input,
and each lane must not have fewer bits that the input lanes. If the and each lane must not have fewer bits that the input lanes. If the
input and output types are the same, this is a no-op. input and output types are the same, this is a no-op.
""", ins=x, outs=a) """, ins=x, outs=a, constraints=WiderOrEq(BoolTo, Bool))
IntTo = TypeVar( IntTo = TypeVar(
'IntTo', 'An integer type with the same number of lanes', 'IntTo', 'An integer type with the same number of lanes',