Return RegInfo by value from TargetIsa::register_info().

The struct is just a pair of static references, and we don't need the
double indirection.

lib/cretonne/src/isa/arm32/mod.rs

@@ -49,8 +49,8 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
-    fn register_info(&self) -> &RegInfo {
+    fn register_info(&self) -> RegInfo {
-        &registers::INFO
+        registers::INFO.clone()
     }
 
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {

lib/cretonne/src/isa/arm64/mod.rs

@@ -42,8 +42,8 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
-    fn register_info(&self) -> &RegInfo {
+    fn register_info(&self) -> RegInfo {
-        &registers::INFO
+        registers::INFO.clone()
     }
 
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {

lib/cretonne/src/isa/intel/mod.rs

@@ -49,8 +49,8 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
-    fn register_info(&self) -> &RegInfo {
+    fn register_info(&self) -> RegInfo {
-        &registers::INFO
+        registers::INFO.clone()
     }
 
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {

lib/cretonne/src/isa/mod.rs

@@ -132,7 +132,7 @@ pub trait TargetIsa {
     fn flags(&self) -> &settings::Flags;
 
     /// Get a data structure describing the registers in this ISA.
-    fn register_info(&self) -> &RegInfo;
+    fn register_info(&self) -> RegInfo;
 
     /// Encode an instruction after determining it is legal.
     ///

lib/cretonne/src/isa/registers.rs

@@ -168,6 +168,7 @@ impl From<RegClass> for RegClassIndex {
 ///
 /// The `RegUnit` data structure collects all relevant static information about the registers in an
 /// ISA.
+#[derive(Clone)]
 pub struct RegInfo {
     /// All register banks, ordered by their `first_unit`. The register banks are disjoint, but
     /// there may be holes of unused register unit numbers between banks due to alignment.

lib/cretonne/src/isa/riscv/mod.rs

@@ -49,8 +49,8 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
-    fn register_info(&self) -> &RegInfo {
+    fn register_info(&self) -> RegInfo {
-        &registers::INFO
+        registers::INFO.clone()
     }
 
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {

lib/cretonne/src/regalloc/liveness.rs

@@ -324,7 +324,7 @@ impl Liveness {
                     // resolved by the coloring algorithm, and ABI constraints require specific
                     // registers or stack slots which the affinities don't model anyway.
                     if let Some(constraint) = operand_constraints.next() {
-                        lr.affinity.merge(constraint, reg_info);
+                        lr.affinity.merge(constraint, &reg_info);
                     }
                 });
             }